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參數(shù)資料
| 型號： | 74LVTH16652MTD |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal Bus Transceivers And Registers With 3-State Outputs 24-SOIC -40 to 85 |
| 中文描述： | LVT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 6.10 MM, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大小： | 87K |
| 代理商： | 74LVTH16652MTD |
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7
AC Electrical Characteristics
Note 9:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
(Note 10)
Note 10:
Capacitance is measured at frequency f
=
1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
T
A
=
40
°
C to
+
85
°
C
C
L
=
50 pF, R
L
=
500
V
CC
=
3.3V
±
0.3V
Min
Max
150
1.3
4.8
1.3
5.1
Units
V
CC
=
2.7V
Min
150
1.3
1.3
Max
f
MAX
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PZL
t
PZH
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PLZ
t
PHZ
t
S
Maximum Clock Frequency
Propagation Delay
CPAB or CPBA to A or B
MHz
5.4
5.6
ns
Propagation Delay
Data to A or B
Propagation Delay
1.0
1.0
1.0
4.5
4.4
4.9
1.0
1.0
1.0
5.1
4.7
5.5
ns
ns
SBA or SAB to A or B
Output Enable Time
1.0
1.0
1.0
4.8
4.9
4.8
1.0
1.0
1.0
5.4
5.8
5.8
ns
OE to A
Output Disable Time
1.6
2.0
5.6
5.4
1.6
2.0
6.1
6.1
ns
OE to A
Output Enable Time
OE to B
1.3
1.3
5.0
4.8
1.3
1.3
5.4
5.4
ns
Output Disable Time
OE to B
Setup Time
1.3
1.3
1.2
5.5
5.6
1.3
1.3
1.5
6.2
6.3
ns
A or B before CPAB or CPBA, Data HIGH
ns
A or B before CPAB or CPBA, Data LOW
A or B before CPAB or CPBA, Data HIGH
A or B before CPAB or CPBA, Data LOW
2.0
0.5
0.5
2.8
0.0
0.5
t
H
Hold Time
ns
t
W
t
OSHL
t
OSLH
Pulse Width
Output to Output Skew (Note 9)
CPAB or CPBA HIGH or LOW
3.3
3.3
ns
1.0
1.0
1.0
1.0
ns
Symbol
Parameter
Conditions
Typical
Units
C
IN
C
I/O
Input Capacitance
Input/Output Capacitance
V
CC
=
Open, V
I
=
0V or V
CC
V
CC
=
3.0V, V
O
=
0V or V
CC
4
8
pF
pF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVTH16652MTD_Q | 功能描述:總線收發(fā)器 16-Bit Trans/Reg RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16652MTDX | 功能描述:總線收發(fā)器 16-Bit Trans/Reg RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH16835_ZAB3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74LVTH16835_ZAB3116B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74LVTH16835DGGRE4 | 功能描述:通用總線函數(shù) 3.3V ABT 18-Bit Univ Bus Drvr W/3-St Otpt RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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