參數(shù)資料
型號: 74LVTH16646
廠商: Fairchild Semiconductor Corporation
英文描述: Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
中文描述: 低電壓16位收發(fā)器/ 3注冊態(tài)輸出
文件頁數(shù): 2/9頁
文件大小: 89K
代理商: 74LVTH16646
www.fairchildsemi.com
2
7
Connection Diagram
Pin Descriptions
Truth Table
(Note 1)
H
=
HIGH Voltage Level
X
=
Immaterial
L
=
LOW Voltage Level
=
LOW-to-HIGH Transition.
Note 1:
The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e.,
data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control
pins.
Pin Names
Description
A
0
–A
15
Data Register A Inputs/3-STATE Outputs
B
0
–B
15
Data Register B Inputs/3-STATE Outputs
CPAB
n
, CPBA
n
Clock Pulse Inputs
SAB
n
, SBA
n
Select Inputs
OE
1
, OE
2
Output Enable Inputs
DIR
n
Direction Control Inputs
Inputs
Data I/O
Output Operation Mode
OE
1
H
H
H
L
L
L
L
L
L
L
L
DIR
1
X
X
X
H
H
H
H
L
L
L
L
CPAB
1
CPBA
1
H or L
SAB
1
X
X
X
L
L
H
H
X
X
X
X
SBA
1
X
X
X
X
X
X
X
L
L
H
H
A
0–7
B
0–7
H or L
X
Isolation
Clock A
n
Data into A Register
Clock B
n
Data Into B Register
A
n
to B
n
—Real Time (Transparent Mode)
Output Clock A
n
Data to A Register
A Register to B
n
(Stored Mode)
Clock A
n
Data into A Register and Output to B
n
B
n
to A
n
—Real Time (Transparent Mode)
Input
Clock B
n
Data into B Register
B Register to A
n
(Stored Mode)
Clock B
n
into B Register and Output to A
n
Input
Input
X
X
X
X
X
X
X
Input
H or L
X
X
X
X
Output
H or L
相關(guān)PDF資料
PDF描述
74LVTH16646MEA Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
74LVTH16646MTD Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
74LVTH16652 Octal Bus Transceivers And Registers With 3-State Outputs 24-PDIP -40 to 85
74LVTH16652MEA Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
74LVTH16652MTD Octal Bus Transceivers And Registers With 3-State Outputs 24-SOIC -40 to 85
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