參數(shù)資料
型號(hào): 74LVTH16373MTDX
廠商: Fairchild Semiconductor
文件頁數(shù): 3/8頁
文件大小: 0K
描述: IC TRANSPRNT LATCH 16BIT 48TSSOP
標(biāo)準(zhǔn)包裝: 1
系列: 74LVTH
邏輯類型: D 型透明鎖存器
電路: 8:8
輸出類型: 三態(tài)
電源電壓: 2.7 V ~ 3.6 V
獨(dú)立電路: 2
延遲時(shí)間 - 傳輸: 1.5ns
輸出電流高,低: 32mA,64mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 74LVTH16373MTDXDKR
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VTH16373
Functional Description
The LVT16373 and LVTH16373 contain sixteen D-type
latches with 3-STATE standard outputs. The device is byte
controlled with each byte functioning identically, but inde-
pendent of the other. Control pins can be shorted together
to obtain full 16-bit operation. The following description
applies to each byte. When the Latch Enable (LEn) input is
HIGH, data on the Dn enters the latches. In this condition
the latches are transparent, i.e, a latch output will change
states each time its D input changes. When LEn is LOW,
the latches store information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LEn. The 3-STATE standard outputs are controlled by
the Output Enable (OEn) input. When OEn is LOW, the
standard outputs are in the 2-state mode. When OEn is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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