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參數(shù)資料
| 型號： | 74LVTH162373MEA |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25з Series Resistors in the Outputs |
| 中文描述： | LVT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | 0.300 INCH, MO-118, SSOP-48 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 78K |
| 代理商： | 74LVTH162373MEA |
www.fairchildsemi.com
2
7
Connection Diagram
Pin Descriptions
Truth Tables
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
HIGH Impedance
O
o
=
Previous output prior to HIGH-to-LOW transition of LE
Functional Description
The LVTH162373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each
byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation.
The following description applies to each byte. When the Latch Enable (LE
n
) input is HIGH, data on the D
n
enters the
latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input changes.
When LE
n
is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW
transition of LE
n
. The 3-STATE standard outputs are controlled by the Output Enable (OE
n
) input. When OE
n
is LOW, the
standard outputs are in the 2-state mode. When OE
n
is HIGH, the standard outputs are in the high impedance mode but
this does not interfere with entering new data into the latches.
Pin Names
Description
OE
n
LE
n
I
0
–I
15
O
0
–O
15
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
3-STATE Outputs
Inputs
Outputs
LE
1
OE
1
I
0
–I
7
O
0
–O
7
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O
o
Inputs
Outputs
LE
2
OE
2
I
8
–I
15
O
8
–O
15
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O
o
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LVTH162373MEX | Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25з Series Resistors in the Outputs |
| 74LVTH162373MTD | Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25з Series Resistors in the Outputs |
| 74LVTH162373MTX | Octal Bus Transceivers With 3-State Outputs 20-SOIC -40 to 85 |
| 74LVTH240MTCX_NL | Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs |
| 74LVTH240 | Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVTH162373MEA_Q | 功能描述:閉鎖 16-Bit Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVTH162373MEX | 功能描述:閉鎖 16-Bit Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVTH162373MTD | 功能描述:閉鎖 16-Bit Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVTH162373MTD_Q | 功能描述:閉鎖 16-Bit Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVTH162373MTX | 功能描述:閉鎖 16-Bit Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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