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參數(shù)資料
| 型號(hào)： | 74LVT16952MTD |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs |
| 中文描述： | LVT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 6.10 MM, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 75K |
| 代理商： | 74LVT16952MTD |
www.fairchildsemi.com
2
7
Connection Diagram
Pin Descriptions
Truth Table
(Note 1)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
Output High Impedance
=
LOW-to-HIGH Transition.
NC
=
No Change (state established by last valid CP)
B
0
=
State established by last valid CP
Note 1:
A to B data flow shown; B to A flow control is the same, but used
OEBA
n
, CPBA
n
and CEB
n
.
Pin Names
Description
A
0
–
A
16
Data Register A Inputs
B-Register 3-STATE Outputs
B
0
–
B
16
Data Register B Inputs
A-Register 3-STATE Outputs
CPAB
n
, CPBA
n
Clock Pulse Inputs
CEA
n
, CEB
n
Clock Enable
OEAB
n
, OEBA
n
Output Enable Inputs
Inputs
Internal Register Output
A
n
CPAB
n
CEA
n
OEAB
n
Value
B
n
X
X
H
L
NC
B
0
Z
X
X
H
H
NC
L
L
L
L
L
L
L
H
L
Z
H
L
L
H
H
H
L
H
H
Z
X
L
X
L
NC
B
0
B
0
Z
X
H
X
L
NC
X
L
X
H
NC
X
H
X
H
NC
Z
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