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參數(shù)資料
| 型號(hào)： | 74LVT16952MEA |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 通用總線(xiàn)功能 |
| 英文描述： | Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs |
| 中文描述： | LVT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.300 INCH, MO-118, SSOP-56 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 75K |
| 代理商： | 74LVT16952MEA |
2001 Fairchild Semiconductor Corporation
DS500103
www.fairchildsemi.com
January 2000
Revised October 2001
7
74LVT16952
74LVTH16952
Low Voltage 16-Bit Registered Transceiver
with 3-STATE Outputs
General Description
The LVT16952 and LVTH16952 are 16-bit registered
transceivers. Two 8-bit back to back registers store data
flowing in both directions between two bidirectional buses.
Separate clock, clock enable, and output enable signals
are provided for each register.
The LVTH16952 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The registered transceiver is designed for low-voltage
(3.3V) V
CC
applications, but with the capability to provide a
TTL interface to a 5V environment.
The LVT16952 and LVTH16952 are fabricated with an
advanced BiCMOS technology to achieve high speed oper-
ation similar to 5V ABT while maintaining low power dissi-
pation.
Features
I
Input and output interface capability to systems at
5V V
CC
I
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16952)
I
Live insertion/extraction permitted
I
Power Up/Down high impedance provides glitch-free
bus loading
I
Outputs source/sink
32 mA/
+
64 mA
I
Functionally compatible with the 74 series 16952
I
Latch-up conforms to JEDEC JED78
I
ESD performance:
Human-body model
>
2000V
Machine model
>
200V
Charged-device model
>
1000V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
74LVT16952MEA
(Preliminary)
74LVT16952MTD
(Preliminary)
74LVTH16952MEA
74LVTH16952MTD
Package Number
MS56A
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MS56A
MTD56
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LVT16952MEAX | Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs |
| 74LVT16952MTD | Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs |
| 74LVT16952MTDX | Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs |
| 74LVTH16952MEAX | Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs |
| 74LVTH16952MTDX | Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs |
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