參數(shù)資料
型號: 74LVT16652
廠商: National Semiconductor Corporation
英文描述: 3.3V ABT 16-Bit Transceiver/Register with TRI-STATE Outputs
中文描述: 3.3生根粉16位收發(fā)器/注冊的三態(tài)輸出
文件頁數(shù): 3/7頁
文件大?。?/td> 125K
代理商: 74LVT16652
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or both.
The select (SAB
n
, SBA
n
) controls can multiplex stored and
real-time.
The examples inFigure 1 demonstrate the four fundamental
bus-management functions that can be performed with the
LVT16652.
Data on the A or B data bus, or both can be stored in the
internal D flip-flop by LOW to HIGH transitions at the appro-
priate Clock Inputs (CPAB
n
, CPBA
n
) regardless of the Se-
lect or Output Enable Inputs. When SAB and SBA are in the
real time transfer mode, it is also possible to store data
without using the internal D flip-flops by simultaneously en-
abling OEAB
n
and OEBA
n
. In this configuration each Output
reinforces its Input. Thus when all other data sources to the
two sets of bus lines are in a HIGH impedance state, each
set of bus lines will remain at its last state.
Real-Time Transfer
Bus B to Bus A
TL/F/12024–4
OEAB
1
OEBA
1
CPAB
1
CPBA
1
SAB
1
SBA
1
L
L
X
X
X
L
Real-Time Transfer
Bus A to Bus B
TL/F/12024–5
OEAB
1
OEBA
1
CPAB
1
CPBA
1
SAB
1
SBA
1
H
H
X
X
L
X
Storage
TL/F/12024–6
OEAB
1
OEBA
1
CPAB
1
CPBA
1
SAB
1
SBA
1
L
X
H
X
X
X
L
X
X
L
X
X
L
H
L
L
X
X
Transfer Storage
Data to A or B
TL/F/12024–7
OEAB
1
OEBA
1
CPAB
1
CPBA
1
SAB
1
SBA
1
H
L
H or L
H or L
H
H
FIGURE 1
Truth Table
(Note)
Inputs
Inputs/Outputs
Operating Mode
OEAB
1
OEBA
1
CPAB
1
CPBA
1
SAB
1
SBA
1
A
0
thru A
7
B
0
thru B
7
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
L
L
L
L
X
X
Store A and B Data
X
H
H or L
X
X
Input
Not Specified
Store A, Hold B
H
H
L
L
L
X
X
Input
Output
Store A in Both Registers
L
X
H or L
X
X
Not Specified
Input
Hold A, Store B
L
L
L
X
X
Output
Input
Store B in Both Registers
L
L
X
X
X
L
Output
Input
Real-Time B Data to A Bus
L
L
X
H or L
X
H
Store B Data to A Bus
H
H
X
X
L
X
Input
Output
Real-Time A Data to B Bus
H
H
H or L
X
H
X
Stored A Data to B Bus
H
L
H or L
H or L
H
H
Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
L
e
LOW to HIGH Clock Transition
Note:
The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the
bus pins will be stored on every LOW to HIGH transition on the clock inputs. This also applies to data I/O (A and B: 8–15) and
Y
2 control pins.
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