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參數(shù)資料
| 型號(hào)： | 74LVT14PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3V Hex inverter Schmitt trigger |
| 中文描述： | LVT SERIES, HEX 1-INPUT INVERT GATE, PDSO14 |
| 封裝： | 4.4 MM, PLASTIC, SOT-402-1, TSSOP-14 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 102K |
| 代理商： | 74LVT14PWDH |
Philips Semiconductors
Product specification
74LVT14
3.3V Hex inverter Schmitt trigger
1996 Aug 28
4
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions
Voltages are referenced to GND (ground = 0V)
PARAMETER
LIMITS
SYMBOL
TEST CONDITIONS
Temp = -40
°
C to +85
°
C
UNIT
MIN
TYP
1
MAX
V
T+
Positive-going threshold
V
CC
= 3.3V
1.5
1.7
2.0
V
V
T–
Negative-going threshold
V
CC
= 3.3V
0.9
1.1
1.3
V
V
T
Hysteresis
V
CC
= 3.3V
0.4
0.6
V
V
IK
Input clamp voltage
V
CC
= 2.7V; I
IK
= –18mA
–1.2
V
V
OH
High-level output voltage
V
CC
= 2.7 to 3.6V; I
OH
= –100
μ
A
V
CC
–0.2
V
V
CC
= 2.7V; I
OH
= –6mA
2.4
V
CC
= 3.0V; I
OH
= –20mA
2.0
V
OL
Low–level output voltage
V
CC
= 2.7V; I
OL
= 100
μ
A
0.2
V
V
CC
= 2.7V; I
OL
= 24mA
0.5
V
CC
= 3.0V; I
OL
= 32mA
0.5
I
I
Input leakage current
V
CC
= 0 or 3.6V; V
I
= 5.5V
10
μ
A
V
CC
= 3.6V; V
I
= V
CC
or GND
±
1
I
OFF
Output off current
V
CC
= 0V; V
I
or V
O
= 0 to 4.5V
±
100
μ
A
I
CCH
Quiescent supply current
V
CC
= 3.6V; Outputs High, V
I
= GND or
V
CC,
I
O =
0
0.02
mA
I
CCL
V
CC
= 3.6V; Outputs Low, V
I
= GND or V
CC,
I
O =
0
1.5
3
I
CC
Additional supply current per input pin
2
V
= 3V to 3.6V; One input at V
CC
–0.6V,
Other inputs at V
CC
or GND
0.2
μ
A
C
I
Input capacitance
V
I
= 3V or 0
3
pF
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
°
C.
2. This is the increase in supply current for each input at the specificed voltage level other than V
CC
or GND
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITION
LIMITS
UNIT
V
CC
= 3.3V
±
0.3V
TYP
3.8
3.2
V
CC
= 2.7V
MAX
6.9
4.1
MIN
1.0
1.0
MAX
5.7
4.5
t
PLH
t
PHL
Propagation delay
An to Yn
Waveform 1
ns
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 2.7V
V
M
V
M
V
M
V
M
Yn
An
t
PHL
t
PLH
SA00341
Waveform 1.
Propagation delay for inverting outputs
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