參數(shù)資料
型號: 74LVT125
廠商: NXP Semiconductors N.V.
英文描述: 3.3V Quad buffer 3-State
中文描述: 3.3四緩沖三態(tài)
文件頁數(shù): 3/15頁
文件大?。?/td> 93K
代理商: 74LVT125
9397 750 14703
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 05 — 10 February 2005
3 of 15
Philips Semiconductors
74LVT125
3.3 V quad buffer; 3-state
6.
Pinning information
6.1 Pinning
6.2 Pin description
(1) The die substrate is attached to the
exposed die pad using conductive die
attach material. It can not be used as
a supply pin or input.
Fig 4.
Pin configuration SO14, SSOP14
and TSSOP14
Fig 5.
Pin configuration DHVQFN14
125
1OE
V
CC
1A
4OE
1Y
4A
2OE
4Y
2A
3OE
2Y
3A
GND
3Y
001aac476
1
2
3
4
5
6
7
8
10
9
12
11
14
13
001aac477
125
Transparent top view
2Y
3A
2A
3OE
2OE
4Y
1Y
4A
1A
4OE
G
3
1
V
C
6
9
5
10
4
11
3
12
2
13
7
8
1
1
terminal 1
index area
GND
(1)
Table 3:
Symbol
1OE
1A
1Y
2OE
2A
2Y
GND
3Y
3A
3OE
4Y
4A
4OE
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
1 output enable input (active LOW)
1 data input
1 data output
2 output enable input (active LOW)
2 data input
2 data output
ground (0 V)
3 data output
3 data input
3 output enable input (active LOW)
4 data output
4 data input
4 output enable input (active LOW)
supply voltage
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