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參數(shù)資料
| 型號(hào)： | 74LVQ573QSC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage Octal Latch with 3-STATE Outputs |
| 中文描述： | LVQ SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | 0.150 INCH, MO-137, QSOP-20 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 75K |
| 代理商： | 74LVQ573QSC |
74LVQ573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS NON INVERTING
February 1999
I
HIGHSPEED:t
PD
=5ns(TYP.)atV
CC
=3.3V
I
COMPATIBLEWITH TTL OUTPUTS
I
LOWPOWERDISSIPATION:
I
CC
=4
μ
A(MAX.) at T
A
=25
o
C
I
LOWNOISE:
V
OLP
=0.5V (TYP.)at V
CC
= 3.3V
I
75
TRANSMISSIONLINEDRIVING
CAPABILITY
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 24mA(MIN)
I
PCIBUSLEVELSGUARANTEED AT24mA
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 2Vto 3.6V(1.2VDataRetention)
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES573
I
IMPROVEDLATCH-UP IMMUNITY
DESCRIPTION
The LVQ573 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology.
It is ideal for low power and low
noise 3.3V applications.
These 8 bit D-Type flip-flops are controlled by a
latch enable input (LE) and an output enable
input (OE).
While the LE input is held at a high level, the Q
outputswill follow the data input precisely.
When the LE is taken low, the Q outputs will be
latchedpreciselyat thelogic level of D input data.
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedancestate.
It has better speed performance at 3.3V than 5V
LSTTL family combined with the true CMOS low
power consumption.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
equipped with
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES :
74LVQ573M
74LVQ573T
M
(Micro Package)
T
(TSSOPPackage)
1/10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LVQ573 | Low Voltage Octal Latch with 3-STATE Outputs |
| 74LVQ573SC | Low Voltage Octal Latch with 3-STATE Outputs |
| 74LVQ573SJ | Low Voltage Octal Latch with 3-STATE Outputs |
| 74LVQ574M | OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING |
| 74LVQ574T | OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVQ573QSC_Q | 功能描述:閉鎖 Octal Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVQ573QSCX | 功能描述:閉鎖 Octal Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVQ573SC | 功能描述:閉鎖 Octal Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVQ573SCX | 功能描述:閉鎖 Octal Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVQ573SJ | 功能描述:閉鎖 Octal Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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