參數(shù)資料
型號: 74LVQ174T
廠商: 意法半導(dǎo)體
英文描述: HEX D-TYPE FLIP FLOP WITH CLEAR
中文描述: 十六進(jìn)制D型觸發(fā)器與清除
文件頁數(shù): 1/10頁
文件大小: 71K
代理商: 74LVQ174T
74LVQ174
HEX D-TYPE FLIP FLOP WITH CLEAR
February 1999
I
HIGHSPEED:
f
MAX
=150MHz(TYP.) at V
CC
=3.3V
I
COMPATIBLEWITH TTL OUTPUTS
I
LOWPOWERDISSIPATION:
I
CC
=4
μ
A(MAX.) at T
A
=25
o
C
I
LOWNOISE:
V
OLP
=0.3V (TYP.)at V
CC
= 3.3V
I
75
TRANSMISSIONLINEDRIVING
CAPABILITY
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 12mA(MIN)
I
PCIBUSLEVELSGUARANTEED AT24mA
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 2Vto 3.6V(1.2VDataRetention)
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES174
I
IMPROVEDLATCH-UP IMMUNITY
DESCRIPTION
The LVQ174 is a low voltage CMOS HEX
D-TYPE
FLIP
FLOP
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology.It is ideal for low power and low noise
WITH
CLEAR
NON
3.3Vapplications.
Information signals applied to D inputs are
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentelyof the other inputs .
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
equipped with
PIN CONNECTION AND IEC LOGIC SYMBOLS
M
(Micro Package)
T
(TSSOPPackage)
ORDER CODES :
74LVQ174M
74LVQ174T
1/10
相關(guān)PDF資料
PDF描述
74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset
74LVQ174SC Low Voltage Hex D-Type Flip-Flop with Master Reset
74LVQ174SJ Low Voltage Hex D-Type Flip-Flop with Master Reset
74LVQ174 Hex D-Type Flip Flop with Clear(帶清除端的六D觸發(fā)器)
74LVQ20 DUAL 4-INPUT NAND GATE
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