參數(shù)資料
型號(hào)： 74LVCH32373A
廠商： NXP Semiconductors N.V.
英文描述： 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state
中文描述： 32位透明D型鎖存與5伏/輸出;三態(tài)耐壓輸入
文件頁(yè)數(shù)： 2/16頁(yè)
文件大?。?/td> 80K
代理商： 74LVCH32373A
1999 Nov 24
2
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
74LVCH32373A
FEATURES
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
MULTIBYTE
flow-trough standard pin-out architecture
Low inductance multiple power and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
Bus hold on data inputs
Typical output ground bounce voltage:
V
OLP
< 0.8 V at V
CC
= 3.3 V and T
amb
= 25
°
C
Typical output undershoot voltage:
V
OHV
> 2 V at V
CC
= 3.3 V and T
amb
= 25
°
C
Power off disables outputs, permitting live insertion
Packaged in plastic fine-pitch ball grid array package.
DESCRIPTION
The 74LVCH32373A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
The inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V. These
features allow the use of these devices in a mixed
3.3 or 5 V environment.
The 74LVCH32373A is a 32-bit transparent D-type latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. One latch enable
(nLE) input and one output enable (nOE) are provided for
each octal. Inputs can be driven from either 3.3 or 5 V
devices.
The 74LVCH32373A consists of 4 sections of eight D-type
transparent latches with 3-state true outputs. When input
nLE is HIGH, data at the nD
n
inputs enter the latches. In
this condition the latches are transparent, i.e. a latch
output will change each time its corresponding D-input
changes.
When input nLE is LOW the latches store the information
that was present at the D-inputs one set-up time preceding
the HIGH-to-LOW transition of nLE. When input nOE is
LOW, the contents of the eight latches are available at the
outputs. When input nOE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the nOE input
does not affect the state of the latches.
The 74LVCH32373A bus hold data input circuits eliminate
the need for external pull-up resistors to hold unused
inputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns.
Note
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay
nD
n
to nQ
n
nLE to nQ
n
input capacitance
power dissipation capacitance
per buffer
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 3.3 V
3.0
3.4
5.0
26
ns
ns
pF
pF
C
I
C
PD
V
I
= GND to V
CC
; note 1
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74LVCH32373AEC 功能描述:閉鎖 32-BIT 5V TOLERANT BUFFER TRAN RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類(lèi)型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
74LVCH32373AEC,518 功能描述:閉鎖 32-BIT 5V TOLERANT RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類(lèi)型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
74LVCH32373AEC,551 功能描述:閉鎖 32-BIT 5V TOLERANT RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類(lèi)型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
74LVCH32373AEC,557 功能描述:閉鎖 32-BIT 5V TOLERANT RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類(lèi)型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
74LVCH32373AEC/G 功能描述:閉鎖 32-BIT 5V TOLERANT BUFFER TRAN RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類(lèi)型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel
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