參數(shù)資料
型號(hào): 74LVCH162245A
廠商: NXP Semiconductors N.V.
英文描述: 16-bit bus transceiver with direction pin;with 30Ω series termination resistors, 5V input/output tolerant (3-State)(帶30Ω串聯(lián)終端電阻器具有定向引腳的5V輸入/輸出容限的16位總線收發(fā)器(三態(tài)))
中文描述: 16位總線收發(fā)器引腳方向;與30Ω串聯(lián)端接電阻器,5V的輸入/輸出寬容(3態(tài))(帶30Ω串聯(lián)終端電阻器具有定向引腳的5V的輸入/輸出容限的16位總線收發(fā)器(三態(tài)))
文件頁數(shù): 2/10頁
文件大小: 84K
代理商: 74LVCH162245A
Philips Semiconductors
Product specification
74LVC162245A/
74LVCH162245A
16-bit bus transceiver with direction pin; 30
series
termination resistors; 5V Input/Outputs tolerant (3-State)
2
1998 Feb 17
853-2012 18974
FEATURES
5 volt tolerant inputs/outputs for interfacing with 5V logic
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum
noise and ground bounce
Direct interface with TTL levels
Bus hold on data inputs (74LVCH162245A only)
Integrated 30
termination resistors
DESCRIPTION
The 74LVC(H)162245A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families. Inputs can be driven from either
3.3V or 5V devices. In 3-State operation, outputs can handle 5V.
These features allow the use of these devices in a mixed 3.3V/5V
environment.
The 74LVC(H)162245A is a 16-bit transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. The 74LVC(H)162245A features two output
enable (nOE) inputs for easy cascading and two send/receive
(nDIR) inputs for direction control. nOE controls the outputs so that
the buses are effectively isolated. The 74LVC(H)162245A is design
with 30
series termination resistors in both HIGH and LOW output
stages to reduce line noise. This device can be used as two 8-bit
transceivers or one 16-bit transceiver.
The 74LVCH162245A bus hold data inputs eliminates the need for
extreme pull up resistors to hold unused inputs.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
GND
V
CC1
GND
GND
V
CC1
2A5
2A4
V
CC2
2A3
2A2
GND
2A1
2A0
1A7
1A6
GND
1A5
1A4
V
CC2
1A3
1A2
GND
1A1
1A0
1OE
21
22
23
24
25
26
27
28
GND
2DIR
2OE
2A7
2A6
GND
SW00198
1DIR
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
OUTSIDE NORTH AMERICA
74LVC162245A DL
74LVC162245A DGG
74LVCH162245A DL
74LVCH162245A DGG
NORTH AMERICA
VC162245A DL
VC162245A DGG
VCH162245A DL
VCH162245A DGG
DWG NUMBER
SOT370-1
SOT362-1
SOT370-1
SOT362-1
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
2.5ns
SYMBOL
Propagation delay
An to Bn;
Bn to An
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
C
L
= 50pF
V
CC
= 3.3V
3.3
ns
C
I
C
I/O
C
PD
Input capacitance
Input/output capacitance
Power dissipation capacitance per buffer
5.0
10
28
pF
pF
pF
V
I
= GND to V
CC1
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
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74LVCH162245ADGG,112 制造商:NXP Semiconductors 功能描述:
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