參數(shù)資料
型號: 74LVC74A
廠商: NXP Semiconductors N.V.
英文描述: Dual D-type flip-flop with set and reset; positive-edge trigger
中文描述: 帶設(shè)置和復(fù)位功能的雙D觸發(fā)器;上升沿觸發(fā)
文件頁數(shù): 6/10頁
文件大?。?/td> 99K
代理商: 74LVC74A
Dual D-type flip-flop with set and reset;
positive-edge trigger
Philips Semiconductors
Product Specification
74LVC74A
1998 Jun 17
6
AC WAVEFORMS
V
M
= 1.5 V at V
CC
V
M
= 0.5 V
CC
at V
CC
< 2.7 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
2.7 V
SV00489
VM
nD INPUT
nCP INPUT
nQ OUTPUT
nQ OUTPUT
VM
VM
VM
tsu
tsu
1/fmax
th
th
tPHL
tPHL
tPLH
tPLH
tW
GND
GND
VI
VI
VOL
VOL
VOH
VOH
NOTE:
The shaded areas indicate when the inputis permitted to change for predictable
output performance.
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,
clock pulse width, nD to nCP set-up times,
the nCP to nD hold times, output transition times
and maximum clock pulse frequency.
SV00490
VM
nCP INPUT
nSD INPUT
nRD INPUT
nQ OUTPUT
nQ OUTPUT
VM
VM
VM
trem
tPHL
tPLH
tW
tW
VM
tPHL
tPLH
GND
GND
GND
VI
VI
VI
VOL
VOL
VOH
VOH
Figure 2. Set (nS
D
) and reset (nR
D
) input to output (nQ, nQ)
propagation delays, the set and reset pulse widths
and the nRD to nCP removal time.
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
V
CC
500
Open
GND
S
1
V
CC
V
I
< 2.7V
V
CC
TEST
S
1
t
PLH/
t
PHL
Open
2.7V
2.7–3.6V
50pF
500
2 * V
CC
SV00903
Figure 3. Load circuitry for switching times.
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