參數(shù)資料
型號： 74LVC652PW
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： Octal transceiver/register with dual enable 3-State
中文描述： LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24
文件頁數(shù)： 3/14頁
文件大?。?/td> 147K
代理商： 74LVC652PW
Philips Semiconductors
Product specification
74LVC652
Octal transceiver/register with dual enable (3-State)
1998 Jul 29
3
PIN CONFIGURATION
SV00767
1
2
3
4
5
6
7
8
9
10
11
12
CPAB
SAB
OEAB
A0
A1
A2
A3
A4
A5
A6
A7
GND
VCC
CPBA
SBA
OEBA
B0
B1
B2
B3
B4
B5
B6
B7
24
23
22
21
20
19
18
17
16
15
14
13
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
CP
AB
‘A’ to ‘B’ clock input
(LOW-to-HIGH, edge-triggered)
2
S
AB
Select ‘A’ to ‘B’ source input
3
OE
AB
Output enable B to A input
(active LOW)
4, 5, 6, 7, 8,
9, 10, 11
A
0
to A
7
‘A’ data inputs/outputs
12
GND
Ground (0V)
20, 19, 18, 17,
16, 15, 14, 13
B
0
to B
7
‘B’ data inputs/outputs
21
OE
BA
S
BA
Output enable A to B input
22
Select ‘B’ to ‘A’ source input
23
CP
BA
‘B’ to ‘A’ clock input
(LOW-to-HIGH, edge-triggered)
24
V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS
DATA I/O *
FUNCTION
OE
AB
L
L
OE
BA
H
H
CP
AB
H or L
↑
↑
↑
CP
BA
H or L
↑
S
AB
X
X
S
BA
X
X
A
0
to A
7
B
0
to B
7
input
input
isolation
store A and B data
X
H
H
H
H or L
↑
↑
↑
X
L
X
X
input
input
un *
output
store A, hold B,
store A in both registers
L
L
X
L
H or L
↑
X
X
X
L
un *
output
input
input
hold A, store B,
store B in both registers
L
L
L
L
X
X
X
H or L
X
X
L
H
output
input
real-time B data to A bus
stored B data to A bus
H
H
H
H
X
H or L
X
X
L
H
X
X
input
output
real-time A data to B bus
stored A data to B bus
H
L
H or L
H or L
H
H
output
output
stored A data to B bus and
stored B data to A bus
*
The data output functions may be enabled or disabled by
various signals at the OE
and OE
inputs. Data input
functions are always enabled, i.e., data at the bus inputs will
be stored on every LOW-to-HIGH transition on the clock
inputs.
= unspecified
= HIGH voltage level
= LOW voltage level
= Don’t care
= LOW–to–HIGH level transition
un
H
L
X
↑
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