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參數(shù)資料
| 型號(hào)： | 74LVC543A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal D-type registered transceiver 3-State |
| 中文描述： | 八路?注冊(cè)收發(fā)3型國(guó)家 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大小： | 104K |
| 代理商： | 74LVC543A |
Philips Semiconductors
Product specification
74LVC543A
Octal D-type registered transceiver (3-State)
2
1998 Jul 31
853-1992 19813
FEATURES
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
Supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8–1A
CMOS low power consumption
Direct interface with TTL levels
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
3-State non-inverting outputs for bus oriented applications
High impedance when V
CC
= 0V
DESCRIPTION
The 74LVC543A is a high–performance, low–power, low–voltage,
Si–gate CMOS device and superior to most advanced CMOS
compatible TTL families.
The 74LVC543A is an octal registered transceiver containing two
sets of D–type latches for temporary storage of the data flow in
either direction. Separate latch enable (LE
AB
, LE
BA
) and output
enable (OE
AB
, OE
BA
) inputs are provided for each register to permit
independent control of inputting and outputting in either direction of
the data flow.
The 74LVC543A contains eight D–type latches, with separate inputs
and controls for each set. For data flow from A to B, for example, the
A–to–B enable (E
AB
) input must be LOW in order to enter data from
A
0
–A
7
or take data from B
0
–B
7
, as indicated in the function table.
With E
AB
LOW, a LOW signal on the A–to–B latch enable (LE
AB
)
input makes the A–to–B latches transparent; a subsequent LOW–to
HIGH transition of the LE
AB
signal puts the A data into the latches
where it is stored and the B outputs no longer change with the A
inputs. With E
AB
and OE
AB
both low, the 3–state B output buffers
are active and display the data present at the outputs of the A
latches
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; T
r
= T
f
≤
2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
A
n
to B
n
C
L
= 50 pF
V
CC
= 3.3V
3.3
ns
C
I
input capacitance
5.0
pF
C
I/O
input/output capacitance
10.0
pF
C
PD
power dissipation capacitance per latch
V
CC
= 3.3V
27
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
x V
CC2
x f
i
+
Σ
(C
L
x V
CC2
x f
o )
where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
Σ
(C
L
x V
CC2
x f
o )
= sum of the outputs
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
OUTSIDE NORTH
AMERICA
74LVC543A D
74LVC543A DB
74LVC543A PW
NORTH AMERICA
PKG DWG. #
24-Pin Plastic Small Outline (SO)
24-Pin Plastic Shrink Small Outline (SSOP) Type II
24-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I
74LVC543A D
74LVC543A DB
7LVC543APW DH
SOT137-1
SOT340-1
SOT355-1
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| 74LVC573 | Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State |
| 74LVC574A | Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVC543ABQ | 制造商:NXP Semiconductors 功能描述:IC OCT D-TYPE TXRX 3-ST DHV |
| 74LVC543ABQ,115 | 功能描述:總線收發(fā)器 OCTAL REG XCVR 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVC543ABQ,118 | 功能描述:總線收發(fā)器 Bus XCVR Single 8-CH 3-ST 24-Pin RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVC543ABQ-G | 功能描述:總線收發(fā)器 OCTAL REG XCVR 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVC543AD | 功能描述:總線收發(fā)器 OCTAL REG XCVR 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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