參數(shù)資料
型號(hào): 74LVC2952A
廠商: NXP Semiconductors N.V.
英文描述: Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 85
中文描述: 八路注冊(cè)5 tranceiver伏/ ouputs三態(tài)耐壓輸入
文件頁數(shù): 2/11頁
文件大?。?/td> 101K
代理商: 74LVC2952A
Philips Semiconductors
Product specification
74LVC2952A
Octal registered tranceiver with 5-volt tolerant
inputs/ouputs (3-State)
2
1998 Jul 29
853-1993 19803
FEATURES
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
Wide supply voltage range of 1.2 V to 3.6 V
In accordance with the JEDEC standard no. 8-1 A
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Flow-through pin-out architecture
3-State outputs
Direct interface with TTL levels
Integrated 30 damping resistor
DESCRIPTION
The 74LVC2952A is a low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families. The
74LVC2952A is an octal non-inverting registered transceiver. Two 8-bit
back to back registers store data flowing in both directions between two
bidirectional busses. Data applied to the inputs is entered and stored on
the rising edge of the clock (CPnn) provided that the clock enable CE
nn
)
is LOW. The data is then present at the 3-State output buffers, but is
only accessible when the output enable input (OE
nn
) is LOW. Data flow
from A inputs to B outputs is the same as for B inputs to A outputs. The
74LVC2952A is identical to the 74LVC2953A but has non-inverting
outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
=t
f
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
CP
nn
to A
n
, B
n
Maximum clock frequency
C
L
= 50 pF;
V
CC
= 3.3 V
4.3
ns
f
max
C
I
C
I/O
C
PD
NOTE:
1
150
MHz
Input capacitance
5
pF
Input/output capacitance
10
pF
Power dissipation capacitance per buffer
V
CC
= 3.3V
1
31
pF
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
24-Pin Plastic SO
–40
°
C to +125
°
C
74LVC2952A D
74LVC2952A D
SOT137-1
24-Pin Plastic SSOP Type II
–40
°
C to +125
°
C
74LVC2952A DB
74LVC2952A DB
SOT340-1
24-Pin Plastic TSSOP Type I
–40
°
C to +125
°
C
74LVC2952A PW
74LVC2952APW DH
SOT355-1
PIN CONFIGURATION
SV01716
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
OE
AB
CP
AB
CE
AB
GND
CE
BA
CP
BA
OE
BA
1
2
3
4
5
6
7
8
9
10
11
12
V
CC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
24
23
22
21
20
19
18
17
16
15
14
13
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
8, 7, 6, 5, 4, 3, 2, 1,
B
0
to B
7
GND
B data inputs/outputs
12
Ground (0 V)
9, 15
OE
AB
,OE
BA
Output enable inputs
(active LOW)
10, 14
CP
AB
, CP
BA
CE
AB
, CE
BA
Clock inputs
11, 13,
Clock enable inputs
16, 17, 18, 19, 20,
21, 22, 23
A
0
to A
7
A data inputs/outputs
24
V
CC
Positive supply voltage
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