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參數(shù)資料
| 型號(hào)： | 74LVC257APWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad 2-input multiplexer with 5 Volt tolerant inputs/outputs 3-State |
| 中文描述： | LVC/LCX/Z SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
| 封裝： | PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 97K |
| 代理商： | 74LVC257APWDH |
Philips Semiconductors
Product specification
74LVC257A
Quad 2-input multiplexer with 5 Volt tolerant
inputs/outputs (3-State)
2
1998 Jul 29
853-2101 19802
FEATURES
Wide supply voltage range of 1.2 to 3.6 V
In accordance with JEDEC standard no. 8-1A
CMOS lower power consumption
Direct interface with TTL levels
Output drive capability 50 transmission lines at 85
°
C
5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC257A is a high-performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC257A is a quad 2-input multiplexer with 3-state outputs,
which select 4 bits of data from two sources and are controlled by a
common data select input (S). The data inputs from source 0 (1l
0
to
4l
0
) are selected when input S is LOW and the data inputs from
source 1 (1l
1
to 4l
1
) are selected when S in HIGH. Data appears at the
outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs.
The 74LVC257A is the logic implementation of a 4-pole, 2-position
switch, where the position of the switch is determined by the logic
levels applied to S. The outputs are forced to a high impedance
OFF-state when OE is HIGH.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
=t
f
≤
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nl
0
, nl
1
to nY
S to nY
C
L
= 50 pF;
V
CC
= 3.3 V
3.9
3.5
ns
C
I
C
PD
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
Input capacitance
5.0
pF
Power dissipation capacitance per channel
V
I
= GND to V
CC1
30
pF
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic SO
–40
°
C to +85
°
C
74LVC257A D
74LVC257A D
SOT109-1
16-Pin Plastic SSOP Type II
–40
°
C to +85
°
C
74LVC257A DB
74LVC257A DB
SOT338-1
16-Pin Plastic TSSOP Type I
–40
°
C to +85
°
C
74LVC257A PW
74LVC257APW DH
SOT403-1
PIN CONFIGURATION
SV00636
1
2
3
4
5
6
S
1I
0
1I
1
IY
2l
0
2l
1
V
CC
OE
4l
0
16
15
14
13
12
11
7
8
GND
3l
1
3Y
10
9
2Y
4l
1
4Y
3l
0
LOGIC SYMBOL
SV00637
1
S
OE
2
1I
0
2I
0
3I
0
4I
0
11
I
2I
1
3I
1
4I
1
3
5
4
1Y
6
7
2Y
10
12
4Y
14
11
9
3Y
13
15
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