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參數資料
| 型號： | 74LVC1G58 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Triple 3-Input Positive-NOR Gates 14-SSOP -40 to 85 |
| 中文描述： | 3個三正輸入或非門 14-SSOP封裝 -40℃到85℃ |
| 文件頁數： | 1/17頁 |
| 文件大?。?/td> | 91K |
| 代理商： | 74LVC1G58 |
1.
General description
The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior
to most advanced CMOS compatible TTL families.
The input can be driven from either 3.3 Vor 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
off
. The I
off
circuitry
disables the output, preventing the damaging backflow current through the device when
it is powered down.
The 74LVC1G175 is a single positive edge triggered D-type flip-flop with individual
data (D) input, clock (CP) input, master reset (MR) input, and Q output.
The master reset (MR) is an asynchronous active LOW input and operate independently
of the clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and
fall times.
2.
Features
I
Wide supply voltage range from 1.65 V to 5.5 V
I
5 V tolerant inputs for interfacing with 5 V logic
I
High noise immunity
I
Complies with JEDEC standard:
N
JESD8-7 (1.65 V to 1.95 V)
N
JESD8-5 (2.3 V to 2.7 V)
N
JESD8B/JESD36 (2.7 V to 3.6 V).
I
±
24 mA output drive (V
CC
= 3.0 V)
I
ESD protection:
N
HBM EIA/JESD22-A114-B exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V.
I
CMOS low power consumption
I
Latch-up performance exceeds 250 mA
I
Direct interface with TTL levels
I
Inputs accept voltages up to 5 V
I
Multiple package options
I
Specified from
40
°
C to +85
°
C and
40
°
C to +125
°
C.
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Rev. 01 — 18 October 2004
Product data sheet
相關PDF資料 |
PDF描述 |
|---|---|
| 74LVC1G57 | Triple 3-Input Positive-NOR Gates 14-SOIC -40 to 85 |
| 74LVC1G19 | Quadruple 2-Input Exclusive-NOR Gates With Open-Drain Outputs 14-SOIC -40 to 85 |
| 74LVC1G17 | 8-Bit Addressable Latches 16-TSSOP -40 to 85 |
| 74LVC1G14 | 8-Bit Addressable Latches 16-SO -40 to 85 |
| 74LVC1G126 | 8-Bit Addressable Latches 16-SO -40 to 85 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 74LVC1G58_09 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low-power configurable multiple function gate |
| 74LVC1G58_1107 | 制造商:DIODES 制造商全稱:Diodes Incorporated 功能描述:CONFIGURABLE MULTIPLE-FUNCTION GATE |
| 74LVC1G58DW | 制造商:DIODES 制造商全稱:Diodes Incorporated 功能描述:CONFIGURABLE MULTIPLE-FUNCTION GATE |
| 74LVC1G58DW-7 | 功能描述:邏輯門 1.65 to 5.5V VCC 1G Conf Multi-Function RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數量:2 線路數量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74LVC1G58FW4 | 制造商:DIODES 制造商全稱:Diodes Incorporated 功能描述:CONFIGURABLE MULTIPLE-FUNCTION GATE |
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