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參數(shù)資料
| 型號： | 74LVC169PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Presettable synchronous 4-bit up/down binary counter |
| 中文描述： | LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大小： | 124K |
| 代理商： | 74LVC169PWDH |
Philips Semiconductors
Product specification
74LVC169
Presettable synchronous 4-bit up/down
binary counter
2
1998 May 20
853-1866 19421
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
In accordance with JEDEC standard no. 8-1A
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Synchronous counting and loading
Up/down counting
Modular 16 binary counter
Two count enable inputs for n-bit cascading
Built-in lookahead carry capability
Presettable for programmable operation
Positive-edge triggered clock
DESCRIPTION
The 74LVC169 is a high-performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
The 74LVC169 is a synchronous presettable binary counter which
features an internal lookahead carry and can be used for high-speed
counting. Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the clock (CP).
The outputs (Q
0
to Q
3
) of the counters may be preset to a HIGH or
LOW level. A LOW level at the parallel enable input (PE) disables
the counting action and causes the data at the data inputs
(D
0
to D
3
) to be loaded into the counter on the positive-going edge
of the clock (provided that the set-up and hold time requirements for
PE are met). Preset takes place regardless of the levels at count
enable inputs (CEP and CET). A low level at the master reset input
(MR) sets all four outputs of the flip-flops (Q
0
to Q
3
) to LOW level
after the next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for PE are
met).
This action occurs regardless of the levels at CP, PE, CET and CEP
inputs This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND gate.
The lookahead carry simplifies serial cascading of the counters.
Both count enable inputs (CEP and CET) must be HIGH to count.
The CET input is fed forward to enable the terminal count output
(TC). The TC output thus enabled will produce a HIGH output pulse
of a duration approximately equal to a HIGH level output of Q
0
. This
pulse can be used to enable the next cascaded stage. The
maximum clock frequency for the cascaded counters is determined
by the CP to TC propagation delay and CEP to CP set-up time,
according to the following formula:
f
max
=
_______________1
tp
(max)
(CP to TC) + t
SU
(CEP to CP)
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; T
R
= T
F
2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
CP to Q
n
CP to TC
CET to TC
C
L
= 50 pF
V
CC
= 3.3V
5.0
6.5
5.3
ns
f
MAX
maximum clock frequency
200
MHz
C
I
input capacitance
5.0
pF
C
PD
power dissipation capacitance per gate
notes 1 and 2
42
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
x V
CC2
x f
i
+
Σ
(C
L
x V
CC2
x f
o )
where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
= supply voltage in V;
Σ
(C
x V
CC2
x f
= sum of the outputs
2. The condition is V
1
= GND to V
CC
ORDERING INFORMATION
PACKAGES
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
OUTSIDE NORTH AMERICA
74LVC169 D
74LVC169 DB
74LVC169 PW
NORTH AMERICA
74LVC169 D
74LVC169 DB
74LVC169PW DH
DWG NUMBER
SOT109-1
SOT338-1
SOT403-1
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參數(shù)描述 |
|---|---|
| 74LVC169PW-T | 功能描述:計(jì)數(shù)器 IC 3.3V SYNC 4-BIT BIN COUNTER RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| 74LVC16T245DGGRE4 | 功能描述:轉(zhuǎn)換 - 電壓電平 16B Bus Trans & Reg RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| 74LVC16T245DGGRG4 | 功能描述:轉(zhuǎn)換 - 電壓電平 16B Dual-Supply Bus Xceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| 74LVC16T245DGVRG4 | 功能描述:轉(zhuǎn)換 - 電壓電平 16B Bus Trans & Reg RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| 74LVC16T245DLRG4 | 功能描述:轉(zhuǎn)換 - 電壓電平 16B Bus Trans & Reg RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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