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參數(shù)資料
| 型號： | 74LVC16245ADGG,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 2/20頁 |
| 文件大小： | 0K |
| 描述： | IC BUS TXRX TRI-ST 16BIT 48TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 975 |
| 系列： | 74LVC |
| 邏輯類型： | 收發(fā)器，非反相 |
| 元件數(shù)： | 2 |
| 每個元件的位元數(shù)： | 8 |
| 輸出電流高，低： | 24mA，24mA |
| 電源電壓： | 1.2 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 管件 |
74LVC_LVCH16245A
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 12 — 13 February 2012
10 of 20
NXP Semiconductors
74LVC16245A; 74LVCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
[1]
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[2]
Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD VCC2 fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(C
L VCC
2
f
o) = sum of the outputs.
11. Waveforms
tdis
disable time
nOE to nAn, nBn; see Figure 8
VCC = 1.2 V
-
11.0
-
ns
VCC = 1.65 V to 1.95 V
1.0
4.9
13.1
1.0
14.7
ns
VCC = 2.3 V to 2.7 V
0.5
2.7
7.1
0.5
7.9
ns
VCC = 2.7 V
1.5
3.4
6.6
1.5
8.5
ns
VCC = 3.0 V to 3.6 V
1.5
3.3
5.6
1.5
7.0
ns
CPD
power
dissipation
capacitance
per input; VI =GND to VCC
VCC = 1.65 V to 1.95 V
-
11.5
-
pF
VCC = 2.3 V to 2.7 V
-
15.2
-
pF
VCC = 3.0 V to 3.6 V
-
18.5
-
pF
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[2]
Max
Min
Max
Measurement points are given in Table 8.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7.
The input (nAn, nBn) to output (nBn, nAn) propagation delays
mna477
nAn, nBn
input
nBn, nAn
output
tPHL
tPLH
GND
VI
VM
VOH
VOL
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