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參數(shù)資料
| 型號(hào)： | 74LVC161 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Data Selectors/Multiplexers With 3-State Outputs 16-TSSOP -40 to 85 |
| 中文描述： | 可預(yù)置同步4位二進(jìn)制計(jì)數(shù)器;異步復(fù)位 |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大?。?/td> | 118K |
| 代理商： | 74LVC161 |
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Philips Semiconductors
Product specification
74LVC161
Presettable synchronous 4-bit binary counter;
asynchronous reset
2
1998 May 20
853-1864 19421
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
In accordance with JEDEC standard no. 8–1A
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Asynchronous reset
Synchronous counting and loading
Two count enable inputs for n–bit cascading
Positive edge–triggered clock
Output drive capability 50 transmission lines @85 C
DESCRIPTION
The 74LVC161 is a high–performance, low–power, low–voltage,
Si–gate CMOS device and superior to most advanced CMOS
compatible TTL families.
The 74LVC161 is a synchronous presettable binary counter which
features an internal look–head carry and can be used for
high–speed counting. Synchronous operation is provided by having
all flip–flops clocked simultaneously on the positive–going edge of
the clock (CP). The outputs (Q
0
to Q
3
) of the counters may be
preset to a HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the data at the
data inputs (D
0
to D
3
) to be loaded into the counter on the
positive–going edge of the clock (provided that the set–up and hold
time requirements for PE are met). Preset takes place regardless of
the levels at count enable inputs (CEP and CET). A low level at the
master reset input (MR) sets all four outputs of the flip–flops
(Q
0
to Q
3
) to LOW level regardless of the levels at CP, PE, CET
and CEP inputs (thus providing an asynchronous clear function).
The look–ahead carry simplifies serial cascading of the counters.
Both count enable inputs (CEP and CET) must be HIGH to count.
The CET input is fed forward to enable the terminal count output
(TC). The TC output thus enabled will produce a HIGH output pulse
of a duration approximately equal to a HIGH level output of Q
0
. This
pulse can be used to enable the next cascaded stage. The
maximum clock frequency for the cascaded counters is determined
by the CP to TC propagation delay and CEP to CP set–up time,
according to the following formula:
f
max
=
____________________1
tp
(max)
(CP to TC) + t
SU
(CEP to CP)
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; T
R
= T
F
SYMBOL
2.5ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
CP to Q
n
CP to TC
MR to Q
n
MR to TC
CET to TC
C
L
= 50 pF
V
CC
= 3.3V
4.9
5.7
5.2
5.7
4.5
ns
f
MAX
maximum clock frequency
200
MHz
C
I
input capacitance
5.0
pF
C
PD
power dissipation capacitance per gate
notes 1 and 2
39
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
x V
CC2
x f
i
+
Σ
(C
L
x V
CC2
x f
o )
where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
Σ
(C
L
x V
CC2
x f
o )
= sum of the outputs
2. The condition is V
1
= GND to V
CC
ORDERING INFORMATION
PACKAGES
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
OUTSIDE NORTH AMERICA
74LVC161 D
74LVC161 DB
74LVC161 PW
NORTH AMERICA
74LVC161 D
74LVC161 DB
74LVC161PW DH
DWG NUMBER
SOT109-1
SOT338-1
SOT403-1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LVC161PWDH | Presettable synchronous 4-bit binary counter; asynchronous reset |
| 74LVC162244A | 16-bit buffer/line driver; with 30Ω series termination resistors, 5V input/output tolerant (3-State)(帶30Ω串聯(lián)終端電阻器，5V輸入/輸出容限的16位緩沖器/線驅(qū)動(dòng)器(三態(tài)）) |
| 74LVCH162244A | 16-bit buffer/line driver; with 30Ω series termination resistors, 5V input/output tolerant (3-State)(帶30Ω串聯(lián)終端電阻器，5V輸入/輸出容限的16位緩沖器/線驅(qū)動(dòng)器（三態(tài)）) |
| 74LVC162244 | 16-bit buffer/line driver; with 30ohm series termination resistors, 5V input/output tolerant 3-State |
| 74LVC162245A | 16-bit bus transceiver with direction pin; 30ohm series termination resistors; 5V Input/Outputs tolerant 3-State |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVC161284 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER |
| 74LVC161284DGGRG4 | 功能描述:接口 - 專(zhuān)用 19-Bit Bus Interface With 3-State Outputs RoHS:否 制造商:Texas Instruments 產(chǎn)品類(lèi)型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| 74LVC161284DLRE4 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:19-BIT BUS INTERFACE |
| 74LVC161284DLRG4 | 功能描述:接口 - 專(zhuān)用 19-Bit Bus Interface RoHS:否 制造商:Texas Instruments 產(chǎn)品類(lèi)型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| 74LVC161284TTR | 功能描述:總線收發(fā)器 Hi-Spd IEEE1284 Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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