參數(shù)資料
型號(hào): 74LVC157APWDH
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Quad 2-input multiplexer
中文描述: LVC/LCX/Z SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16
封裝: PLASTIC, TSSOP-16
文件頁數(shù): 2/10頁
文件大小: 93K
代理商: 74LVC157APWDH
Philips Semiconductors
Product specification
74LVC157A
Quad 2-input multiplexer
2
1998 Jul 29
853-1945 19802
FEATURES
Wide supply voltage range of 1.2 to 3.6 V
In accordance with JEDEC standard no. 8-1A
CMOS lower power consumption
Direct interface with TTL levels
5 Volt tolerant inputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC157A is a high-performance, low-power, Si-gate CMOS
device, superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC157A is a quad 2-input multiplexer which select 4 bits of
data from two sources under the control of a common data select
input (S). The four outputs present the selected data in the true
(non-inverted) form. The enable input (E) is active LOW. When E is
HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all
other input conditions. Moving the data from two groups of registers
to four common output buses is a common use of the 74LV157. The
state of the common data select input (S) determines the particular
register from which the data comes. It can also be used as function
generator.
The device is useful for implementing highly irregular logic by
generating any four of the 16 different functions of two variables with
one variable common.
The 74LVC157A is the logic implementation of a 4-pole, 2-position
switch, where the position of the switch is determined by the logic
levels applied to S.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nl
, nl1, to nY
E to nY
S to nY
C
L
= 50 pF;
V
CC
= 3.3 V
3.1
3.0
3.3
ns
C
I
C
PD
Input capacitance
5.0
pF
Power dissipation capacitance per gate
V
I
= GND to V
CC1
33
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic SO
74LVC157A D
74LVC157A D
SOT109-1
16-Pin Plastic SSOP Type II
74LVC157A DB
74LVC157A DB
SOT338-1
16-Pin Plastic TSSOP Type I
74LVC157A PW
74LVC157APW DH
SOT403-1
PIN CONFIGURATION
SV00563
1
2
3
4
5
6
S
1I0
1I1
1Y
2I0
2I1
VCC
E
4I0
4I1
4Y
3I0
16
15
14
13
12
11
7
8
2Y
GND
3I1
3Y
10
9
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
S
Common data select input
2, 5, 11, 14
1l
0
to 4l
0
1l
1
to 4l
1
1Y to 4Y
Data inputs from sources 0
3, 6, 10, 13
Data inputs from sources 1
4, 7, 9, 12
Multiplexer outputs
8
GND
Ground (0 V)
15
E
Enable input (active LOW)
16
V
CC
Positive supply voltage
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