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參數(shù)資料
| 型號： | 74LVC138A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Data Selectors/Multiplexers With 3-State Outputs 16-PDIP -40 to 85 |
| 中文描述： | 3至8線路解碼器/解復(fù)用器;反相 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 94K |
| 代理商： | 74LVC138A |
Philips Semiconductors
Product specification
74LVC138A
3-to-8 line decoder/demultiplexer; inverting
2
1998 Apr 28
853–1943 19308
FEATURES
Wide supply voltage range of 1.2 to 3.6 V
In accordance with JEDEC standard no. 8-1A
Inputs accept voltages up to 5.5 V
CMOS lower power consumption
Direct interface with TTL levels
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
Output drive capability 50 transmission lines at 85
°
C
DESCRIPTION
The 74LVC138A is a low-voltage, low-power, high-performance
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The 74LVC138A accepts three binary weighted address inputs (A
0
,
A
1
, A
2
) and when enabled, provides 8 mutually exclusive active
LOW outputs (Y
0
to Y
7
).
The 74LVC138A features three enable inputs: two active LOW (E
1
and E
2
) and one active HIGH (E
3
). Every output will be HIGH unless
E
1
and E
2
are LOW and E
3
is HIGH.
This multiple enable function allows easy parallel expansion of the
74LV138A to a 1-of-32 (5 lines to 32 lines) decoder with just four
74LV138A ICs and one inverter. The 74LV138A can be used as an
eight output demultiplexer by using one of the active LOW enable
inputs as the data input and the remaining enable inputs as strobes.
Unused enable inputs must be permanently tied to their appropriate
active HIGH or LOW state.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An to Yn,
E
3
to Yn, En to Yn
Input capacitance
C
L
= 50 pF;
V
CC
= 3.3 V
3.5
3.5
ns
C
I
5.0
pF
C
PD
Power dissipation capacitance per
package
V
CC
= 3.3 V
Notes 1 and 2
44
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic SO
–40
°
C to +85
°
C
74LVC138A D
74LVC138A D
SOT109-1
16-Pin Plastic SSOP Type II
–40
°
C to +85
°
C
74LVC138A DB
74LVC138A DB
SOT338-1
16-Pin Plastic TSSOP Type I
–40
°
C to +85
°
C
74LVC138A PW
74LVC138APW DH
SOT403-1
PIN CONFIGURATION
SV00553
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
Y
7
Y
0
A
0
A
1
A
2
E
1
E
2
E
3
V
CC
Y
0
Y
0
Y
0
Y
0
Y
0
Y
0
LOGIC DIAGRAM
SV00554
Y
0
A
0
Y
1
A
1
Y
2
A
2
Y
3
Y
4
Y
5
Y
6
Y
7
15
14
13
12
11
10
E
1
E
2
E
3
9
7
4
1
5
2
6
3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVC138ABQ | 制造商:NXP Semiconductors 功能描述:IC 3-8 LINE DECODER/DEMUX DH |
| 74LVC138ABQ,115 | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3-TO-8 LINE DECODER RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| 74LVC138ABQ-G | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3-TO-8 LINE DECODER DEMUX RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| 74LVC138ABQ-Q100X | 制造商:NXP Semiconductors 功能描述:74LVC138ABQ-Q100/DHVQFN16/REEL - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC DECODER/DEMUX INV 16DHVQFN |
| 74LVC138AD | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3-8 LINE DCOD/DMUX INVERTING RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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