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參數(shù)資料
| 型號(hào)： | 74LVC109PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual JK flip-flop with set and reset; positive-edge trigger |
| 中文描述： | LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | PLASTIC, TSSOP1-16 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 103K |
| 代理商： | 74LVC109PWDH |
Philips Semiconductors
Product specification
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
1998 Apr 28
6
AC WAVEFORMS
V
M
= 1.5 V at V
CC
≥
2.7 V; V
M
= 0.5
×
V
CC
at V
CC
< 2.7 V.
V
OL
and V
OH
are the typical output voltage drop that occur with the output load.
The shaded areas indicate when the input is permitted to change
for predictable output performance.
SV00522
1/fmax
th
th
tPLH
tPHL
tPLH
tPHL
tW
tsu
tsu
VM
VM
VM
VM
nJ, nK
INPUT
GND
nCP
INPUT
GND
nQ
OUTPUT
VI
VI
VOH
VOH
nQ
OUTPUT
VOL
VOL
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,
the clock pulse width, the nJ and nK to nCP set-up,
the nCP to nJ, nK hold times
and the maximum clock pulse frequency.
SV00523
t
W
t
W
t
PLH
t
PHL
t
rem
V
M
V
M
V
M
V
M
V
M
nS
D
INPUT
GND
nR
D
INPUT
GND
nCP
INPUT
GND
nQ
OUTPUT
V
OH
nQ
V
l
V
l
V
l
V
OH
V
OL
V
OL
OUTPUT
t
rem
t
PLH
t
PHL
Figure 2. Set (nS
D
) and reset (nR
D
) input to output (nQ, nQ)
propagation delays, the set and reset pulse widths
and the nR
D
, nS
D
to nCP removal time.
TEST CIRCUIT
V
M
V
M
t
W
NEGATIVE
PULSE
10%
10%
90%
90%
0V
V
M
V
M
t
W
V
I
POSITIVE
PULSE
90%
90%
10%
10%
0V
t
THL
(t
f
)
t
TLH
(t
r
)
t
THL
(t
f
)
t
TLH
(t
r
)
V
M
= 1.5V
Input Pulse Definition
SWITCH POSITION
PULSE
GENERATOR
R
T
V
l
D.U.T.
V
O
C
L
R
L
V
cc
R
L
Test Circuit for Outputs
Open
GND
S
1
DEFINITIONS
V
CC
V
I
< 2.7V
2.7–3.6V
≥
4.5 V
V
CC
2.7V
V
CC
TEST
S
1
t
PLH/
t
PHL
Open
R
L
= Load resistor; see AC CHARACTERISTICS for value.
C
= Load capacitance includes jig and probe capacitance:
See AC CHARACTERISTICS for value.
R
= Termination resistance should be equal to Z
OUT
of
pulse generators.
V
I
SV00904
2
V
CC
Figure 3. Load circuitry for switching times.
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| 74LVC109PW-T | 功能描述:觸發(fā)器 3.3V DUAL JK SET RESET POS RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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| 74LVC10ABQ | 制造商:NXP Semiconductors 功能描述:Bulk 制造商:NXP Semiconductors 功能描述:IC TRPL 3 I/P NAND GATE DHV |
| 74LVC10ABQ,115 | 功能描述:邏輯門 TRIPLE 3-INPUT NAND RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74LVC10ABQ-G | 功能描述:邏輯門 TRIPLE 3-INPUT NAND RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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