參數(shù)資料
型號(hào): 74LV74PW,112
廠商: NXP Semiconductors
文件頁數(shù): 15/19頁
文件大?。?/td> 0K
描述: IC DUAL D FF POSEDG TRIG 14TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,400
系列: 74LV
功能: 設(shè)置(預(yù)設(shè))和復(fù)位
類型: D 型
輸出類型: 差分
元件數(shù): 2
每個(gè)元件的位元數(shù): 1
頻率 - 時(shí)鐘: 56MHz
觸發(fā)器類型: 正邊沿
輸出電流高,低: 12mA,12mA
電源電壓: 1 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 管件
74LV74
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 9 September 2013
5 of 19
NXP Semiconductors
74LV74
Dual D-type flip-flop with set and reset; positive-edge trigger
6.
Functional description
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH clock transition;
Qn+1 = state after the next LOW-to-HIGH CP transition
7.
Limiting values
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
Ptot derates linearly with 12 mW/K above 70 C.
[3]
Ptot derates linearly with 8 mW/K above 70 C.
[4]
Ptot derates linearly with 5.5 mW/K above 60 C.
Table 3.
Function table[1]
Input
Output
nSD
nRD
nCP
nD
nQ
Qn+1
nQn+1
LH
X
H
L-
-
HL
X
L
H-
-
L
XXH
H
-
HH
L-
-
LH
HH
H-
-
HL
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
0.5
+7
V
IIK
input clamping current
VI < 0.5 V or VI >VCC +0.5 V
-
20
mA
VI
input voltage
0.5
+7
V
IOK
output clamping current
VO >VCC or VO < 0
-
50
mA
IO
output current
0.5 V < V
O < VCC +0.5 V
-
25
mA
ICC
supply current
-
50
mA
IGND
ground current
-
50
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
Tamb = 40 C to +125 C
DIP16 package
750
mW
SO16 package
500
mW
(T)SSOP16 package
400
mW
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