- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360490 > 74LV74 (NXP Semiconductors N.V.) Dual D-type flip-flop with set and reset;positive-edge trigger(上升沿觸發(fā),帶置位和復(fù)位的雙D觸發(fā)器) PDF資料下載
參數(shù)資料
| 型號： | 74LV74 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual D-type flip-flop with set and reset;positive-edge trigger(上升沿觸發(fā),帶置位和復(fù)位的雙D觸發(fā)器) |
| 中文描述： | 雙D型觸發(fā)器設(shè)置和復(fù)位觸發(fā)器，積極邊緣觸發(fā)（上升沿觸發(fā)，帶置位和復(fù)位的雙?觸發(fā)器） |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 125K |
| 代理商： | 74LV74 |
Philips Semiconductors
Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
1998 Apr 20
7
AC WAVEFORMS
V
M
= 1.5V at V
CC
V
M
= 0.5 * V
CC
at V
CC
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
2.7V
3.6V
2.7V and
4.5V
GND
h
h
nQ OUTPUT
nD INPUT
nCP INPUT
nQ OUTPUT
V
M
V
M
V
M
t
su
1/f
max
t
PHL
t
PHL
t
PLH
t
PLH
t
W
GND
V
I
V
I
V
OL
V
OL
V
OH
V
OH
t
su
SV00335
Figure 1.The clock (nCP) to output (nQ, nQ) propagation
delays, the clock pulse width, the nD to nCP setup times, the
nCP to nD hold times, the output transition times and the
maximum clock pulse frequency
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
nCP INPUT
nS
D
INPUT
nR
D
INPUT
nQ OUTPUT
nQ OUTPUT
GND
GND
GND
V
I
V
I
V
I
V
OL
V
OL
V
OH
V
OH
V
M
V
M
V
M
V
M
t
rem
t
PHL
t
PLH
t
W
t
W
V
M
t
PLH
t
PHL
SV00336
Figure 2.The set (nS
D
) and reset (nR
D
) input to output (nQ, nQ)
propagation delays, the set and reset pulse widths and the nR
D
to nCP removal time
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
l
D.U.T.
V
O
C
L
R
L
= 1k
V
cc
Test Circuit for Outputs
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitiance
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
V
CC
V
I
< 2.7V
2.7–3.6V
V
CC
2.7V
TEST
t
PLH/
t
PHL
≥
4.5 V
V
CC
50pF
SV00902
Figure 3. Load circuitry for switching times
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LV74PWDH | Dual D-type flip-flop with set and reset; positive-edge trigger |
| 74LV86DB-T | Quad 2-input Exclusive OR (XOR) Gate |
| 74LV86D-T | Quad 2-input Exclusive OR (XOR) Gate |
| 74LV86PW-T | Quad 2-input Exclusive OR (XOR) Gate |
| 74LV86PWDH | Quad 2-input EXCLUSIVE-OR gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV74A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS |
| 74LV74AFP-E | 制造商:Renesas Electronics Corporation 功能描述:Cut Tape |
| 74LV74D | 功能描述:觸發(fā)器 DUAL D-TYPE POS EDGE-TRIG RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LV74D,112 | 功能描述:觸發(fā)器 DUAL D-TYPE POS RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LV74D,118 | 功能描述:觸發(fā)器 DUAL D-TYPE POS RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。