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參數(shù)資料
| 型號(hào)： | 74LV574PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal D-type flip-flop; positive edge-trigger 3-State |
| 中文描述： | LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 121K |
| 代理商： | 74LV574PWDH |
Philips Semiconductors
Product specification
74LV574
Octal D-type flip-flop; positive edge-trigger (3-State)
1998 Jun 10
7
AC WAVEFORMS
V
M
= 1.5V at V
CC
V
M
= 0.5 * V
CC
at V
CC
V
and V
OH
are the typical output voltage drop that occur with the
output load.
V
X
= V
OL
+ 0.3V at V
CC
2.7V and
V
X
= V
OL
+ 0.1V
CC
at V
CC
<
2.7V and
V
Y
= V
OH
– 0.3V at V
CC
2.7V and
V
Y
= V
OH
– 0.1V
CC
at V
CC
<
2.7V and
2.7V and
2.7V and
3.6V
4.5V
3.6V
4.5V
3.6V
4.5V
SV00718
GND
V
OL
V
I
V
OH
V
M
CP INPUT
Q
n
OUTPUT
V
M
t
PLH
t
PHL
1/f
max
t
W
Figure 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse (CP) and the maximum clock pulse frequency
outputs
disabled
SV00344
V
I
OE INPUT
GND
V
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
V
M
t
PLZ
t
PHZ
t
PZL
V
Y
outputs
enabled
outputs
enabled
V
X
V
M
t
PZH
V
M
Figure 2. 3-state enable and disable times
tsu
tsu
SV00345
CP INPUT
D
n
INPUT
Q
n
OUTPUT
V
M
t
h
V
M
V
M(1)
t
h
V
I
GND
V
I
GND
V
OH
V
OL
NOTE:
the shaded areas indicate when the input is permitted to change
for predictable output performance.
Figure 3. Data set-up and hold times for the Dn input to the CP
input
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
R
L
= 1k
V
CC
Test Circuit for Outputs
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitiance.
V
CC
V
I
< 2.7V
V
CC
TEST
t
PLH/
t
PHL
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
2.7V
2.7–3.6V
4.5V
V
CC
50 pF
SV00896
S
1
t
PLZ/
t
PZL
t
PHZ/
t
PZH
Open
2 * V
CC
GND
R
L
= 1k
Open
GND
2 * V
CC
Figure 4. Load circuitry for switching times
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相關(guān)代理商/技術(shù)參數(shù) |
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| 74LV574PW-T | 功能描述:觸發(fā)器 3.3V D-TYPE F/F POS EDGE 3-S RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LV595 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit serial-in/serial or parallel-out shift register with output latches 3-State |
| 74LV595A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS |
| 74LV595APW | 制造商:Texas Instruments 功能描述: 制造商:undefined 功能描述: |
| 74LV595D | 功能描述:計(jì)數(shù)器移位寄存器 8-BIT SHIFT REG W/OUTPUT LATCH RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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