參數(shù)資料
型號(hào): 74LV574
廠商: NXP Semiconductors N.V.
英文描述: Octal D-type flip-flop; positive edge-trigger 3-State
中文描述: 八路D型觸發(fā)器;上升沿觸發(fā)三態(tài)
文件頁數(shù): 7/12頁
文件大小: 121K
代理商: 74LV574
Philips Semiconductors
Product specification
74LV574
Octal D-type flip-flop; positive edge-trigger (3-State)
1998 Jun 10
7
AC WAVEFORMS
V
M
= 1.5V at V
CC
V
M
= 0.5 * V
CC
at V
CC
V
and V
OH
are the typical output voltage drop that occur with the
output load.
V
X
= V
OL
+ 0.3V at V
CC
2.7V and
V
X
= V
OL
+ 0.1V
CC
at V
CC
<
2.7V and
V
Y
= V
OH
– 0.3V at V
CC
2.7V and
V
Y
= V
OH
– 0.1V
CC
at V
CC
<
2.7V and
2.7V and
2.7V and
3.6V
4.5V
3.6V
4.5V
3.6V
4.5V
SV00718
GND
V
OL
V
I
V
OH
V
M
CP INPUT
Q
n
OUTPUT
V
M
t
PLH
t
PHL
1/f
max
t
W
Figure 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse (CP) and the maximum clock pulse frequency
outputs
disabled
SV00344
V
I
OE INPUT
GND
V
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
V
M
t
PLZ
t
PHZ
t
PZL
V
Y
outputs
enabled
outputs
enabled
V
X
V
M
t
PZH
V
M
Figure 2. 3-state enable and disable times
tsu
tsu
SV00345
CP INPUT
D
n
INPUT
Q
n
OUTPUT
V
M
t
h
V
M
V
M(1)
t
h
V
I
GND
V
I
GND
V
OH
V
OL
NOTE:
the shaded areas indicate when the input is permitted to change
for predictable output performance.
Figure 3. Data set-up and hold times for the Dn input to the CP
input
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
R
L
= 1k
V
CC
Test Circuit for Outputs
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitiance.
V
CC
V
I
< 2.7V
V
CC
TEST
t
PLH/
t
PHL
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
2.7V
2.7–3.6V
4.5V
V
CC
50 pF
SV00896
S
1
t
PLZ/
t
PZL
t
PHZ/
t
PZH
Open
2 * V
CC
GND
R
L
= 1k
Open
GND
2 * V
CC
Figure 4. Load circuitry for switching times
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