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參數(shù)資料
| 型號： | 74LV4060PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 14-stage binary ripple counter with oscillator |
| 中文描述： | LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 165K |
| 代理商： | 74LV4060PWDH |
Philips Semiconductors
Product specification
74LV4060
14-stage binary ripple counter with oscillator
1998 Jun 23
12
C3
R
bias
100 k to 1 M
RS
11
R
TC
10
MR (from logic)
C2
100 pF
22 to
37 pF
R2
2.2 k
SV00326
Figure 5. External components connection for
a typical crystal oscillator
R2 is the power limiting resistor. For starting and maintaining
oscillation, a minimum transconductance is necessary, so R2 should
not be too large. A practical value for R2 is 2.2 k .
V
M
CP INPUT
Q
n
OUTPUT
V
OL
V
OH
GND
V
I
V
M
t
PLH
t
PHL
tW
1/
fmax
SV00322
Figure 6.
Waveforms showing the clock (RS) to output (Q
3
) propagation
delays, the clock pulse width, the output transition times and the
maximum clock frequency.
V
M
MR INPUT
RS INPUT
V
I
V
CC
V
I
GND
GND
GND
Qn OUTPUT
V
M
t
rem
t
PHL
t
W
V
M
SV00329
Figure 7.
Waveforms showing the master reset (MR) pulse width, the master
reset to output (Q
n)
propagation delays and the master reset to
clock (RS) removal time.
V
M
Q
n
OUTPUT
V
OH
V
OH
V
OL
V
OL
Q
n+1
OUTPUT
V
M
t
PLH
t
PHL
SV00327
Figure 8.
Waveforms showing the output Q
n
to output
n + 1
propagation
delays.
NOTES:
1. V
M
= 1.5 V at V
CC
> 2.7 V and < 3.6 V
V
M
= 0.5
.
V
CC
at V
CC
< 2.7 V and > 4.5 V.
2. V
and V
are the typical output voltage drop that occur with
the output load.
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