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參數(shù)資料
| 型號： | 74LV4052PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 多路復(fù)用及模擬開關(guān) |
| 英文描述： | Dual 4-channel analog multiplexer/demultiplexer |
| 中文描述： | DUAL 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDSO16 |
| 封裝： | PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 154K |
| 代理商： | 74LV4052PWDH |
Philips Semiconductors
Product specification
74LV4052
Dual 4-channel analog multiplexer/demultiplexer
2
1998 Jun 23
853-1999 19618
FEATURES
Optimized for low voltage applications: 1.0 to 6.0 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Low typ “ON” resistance:
60 at V
cc
– V
EE
= 4.5 V
90 at V
cc
– V
EE
= 3.0 V
145
at V
cc
– V
EE
= 2.0 V
Logic level translation: to enable 3 V logic to communicate with
±
3
V analog signals
Typical “break before make” built in
Analog/Digital multiplexing and demultiplexing
Signal gating
Output capability: non-standard
I
CC
category: MSI
DESCRIPTION
The 74LV4052 is a low-voltage CMOS device and is pin and
function compatible with the 74HC/HCT4052.
The 74LV4052 is a dual 4-channel analog multiplexer/demultiplexer
with a common select logic. Each multiplexer has four independent
inputs/outputs (nY
0
to nY
3
) and a common input/output (nZ). The
common channel select logics include two digital select inputs (S
0
and S
1
) and an active LOW enable input (E).
With E LOW, one of the four switches is selected (low impedance
ON-state) by S
0
and S
1.
With E HIGH, all switches are in the high
impedance OFF-state, independent of S
0
and S
1
. V
CC
and GND are
the supply voltage pins for the digital control inputs (S
0
, S
1
and E).
The V
CC
to GND ranges are 1.0 to 6.0 V. The analog inputs/outputs
(nY
0
, to nY
3
, and nZ) can swing between V
CC
as a positive limit and
V
EE
as a negative limit. V
CC
- V
EE
may not exceed 6.0 V. For
operation as a digital multiplexer/demultiplexer, V
EE
is connected to
GND (typically ground).
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
=t
f
≤
2.5 ns
SYMBOL
Turn “ON” time
E or V
OS
S
n
Turn “OFF” time
E or V
OS
S
n
C
I
Input capacitance
C
PD
Power dissipation capacitance per switch
Maximum switch capacitance
independent (Y) common (Z)
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
((C
L +
C
S
)
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; C
S
= maximum switch capacitance in pF;
V
CC
= supply voltage in V;
((C
L
+C
S
)
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PZH
/t
PZL
C
L
= 15 pF
R
L
= 1K
V
CC
= 3.3 V
3 3 V
30
ns
t
PHZ
/t
PLZ
22
3.5
57
5
12
See Notes 1 and 2
pF
C
S
ORDERING INFORMATION
PACKAGES
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
OUTSIDE NORTH AMERICA
74LV4052 N
74LV4052 D
74LV4052 DB
74LV4052 PW
NORTH AMERICA
74LV4052 N
74LV4052 D
74LV4052 DB
74LV4052PW DH
Code
SOT38-4
SOT109-1
SOT338-1
SOT403-1
PIN CONFIGURATION
SV01697
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16
GND
V
CC
2Y
0
2Y
2
2Z
2Y
3
2Y
1
E
V
EE
1Y
2
1Y
1
1Z
1Y
0
1Y
3
S
0
S
1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1, 5, 2, 4
2Y
0
, 2Y
3
E
Independent inputs/outputs
6
Enable input (active LOW)
7
V
EE
GND
Negative supply voltage
8
Ground (0 V)
10, 9
S
0
, S
1
1Y
0
to 1Y
3
1Z, 2Z
Select inputs
12, 14, 15, 11
Independent inputs/outputs
13, 3
Common inputs/outputs
16
V
CC
Positive supply voltage
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