參數(shù)資料
型號: 74LV4051
廠商: NXP Semiconductors N.V.
英文描述: 8-channel analog multiplexer/demultiplexer(八通道模擬多路復(fù)用器/多路分解器)
中文描述: 8通道模擬多路復(fù)用器/解復(fù)用器(八通道模擬多路復(fù)用器/多路分解器)
文件頁數(shù): 2/18頁
文件大?。?/td> 156K
代理商: 74LV4051
Philips Semiconductors
Product specification
74LV4051
8-channel analog multiplexer/demultiplexer
2
1998 Jun 23
853-1998 19618
FEATURES
Optimized for low voltage applications: 1.0 to 6.0 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Low typ “ON” resistance:
60 at V
cc
– V
EE
= 4.5 V
90 at V
cc
– V
EE
= 3.0 V
145
at V
cc
– V
EE
= 2.0 V
Logic level translation: to enable 3 V logic to communicate with
±
3
V analog signals
Typical “break before make” built in
Output capability: non-standard
I
CC
category: MSI
DESCRIPTION
The 74LV4051 is a low-voltage CMOS device and is pin and
function compatible with the 74HC/HCT4051.
The 74LV4051 is an 8-channel analog multiplexer/demultiplexer with
three digital select inputs (S
0
to S
2
) an active LOW enable input (E),
eight independent inputs/outputs (Y
0
to Y
7
) and a common
input/output (Z).
With E LOW, one of the eight switches is selected (low impedance
ON-state) by S
0
to S
2.
With E HIGH, all switches are in the high
impedance OFF-state, independent of S
0
to S
2
.
V
and GND are the supply voltage pins for the digital control
inputs (S
0
to S
2
, and E). The V
CC
to GND ranges are 1.0 to 6.0 V.
The analog inputs/outputs (Y
to Y
and Z) can swing between V
CC
as a positive limit and V
as a negative limit. V
- V
may not
exceed 6.0 V. For operation as a digital multiplexer/demultiplexer,
V
EE
is connected to GND (typically ground).
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
=t
f
2.5 ns
SYMBOL
Turn “ON” time
E to V
OS
S
n
to V
OS
Turn “OFF” time
E to V
OS
S
n
to V
OS
C
I
Input capacitance
C
PD
Power dissipation capacitance per switch
Maximum switch capacitance
independent (Y) common (Z)
NOTES:
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
((C
L +
C
S
)
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; C
S
= maximum switch capacitance in pF;
V
CC
= supply voltage in V;
((C
L
+C
S
)
×
V
CC2
×
f
o
) = sum of the outputs.
2.
The condition is V
I
= GND to V
CC
.
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PZH
/t
PZL
C
L
= 15 pF
R
L
= 1K
V
CC
= 3.3 V
23
22
ns
t
PHZ
/t
PLZ
25
20
3.5
25
5
25
See Notes 1 and 2
pF
F
C
S
ORDERING INFORMATION
PACKAGES
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
OUTSIDE NORTH AMERICA
74LV4051 N
74LV4051 D
74LV4051 DB
74LV4051 PW
NORTH AMERICA
74LV4051 N
74LV4051 D
74LV4051 DB
74LV4051PW DH
Code
SOT38-4
SOT109-1
SOT338-1
SOT403-1
PIN CONFIGURATION
SV01702
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16
GND
V
CC
Y
4
Y
6
Z
Y
7
Y
5
E
V
EE
Y
2
Y
1
Y
0
Y
3
S
0
S
1
S
2
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
3
Z
Common input/output
6
E
Enable input (active LOW)
7
V
EE
GND
Negative supply voltage
8
Ground (0 V)
11, 10, 9
S
0
to S
2
Select inputs
13, 14, 15, 12,
1, 5, 2, 4
Y
0
to Y
7
Independent inputs/outputs
16
V
CC
Positive supply voltage
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