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參數(shù)資料
| 型號： | 74LV393PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 4-bit binary ripple counter |
| 中文描述： | LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14 |
| 封裝： | PLASTIC, SOT-402, TSSOP1-14 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 115K |
| 代理商： | 74LV393PWDH |
Philips Semiconductors
Product specification
74LV393
Dual 4-bit binary ripple counter
1998 Jun 10
7
AC WAVEFORMS
V
M
= 1.5V at V
CC
V
M
= 0.5 * V
CC
at V
CC
V
and V
OH
are the typical output voltage drop that occur with the
output load.
2.7V
2.7V
SV00678
V
M
nCP INPUT
V
CC
GND
V
OH
V
OL
nQ
n
OUTPUT
V
M
t
PLH
t
PHL
1/f
max
Figure 1. Clock (nCP) to output (1Qn, 2Qn) propagation delays,
the clock pulse width, and the maximum clock frequency
SV00679
V
M
nMR INPUT
nCP INPUT
V
CC
V
CC
GND
GND
V
OL
V
OH
nQ
n
OUTPUT
V
M
V
M
t
rem
t
PHL
t
W
Figure 2. Master reset (nMR) pulse width,
the master reset to output (Qn) propagation delays,
and the master reset to clock (nCP) removal time
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
R
L
= 1k
V
CC
Test Circuit for switching times
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitance
V
CC
V
I
< 2.7V
V
CC
TEST
t
PLH/
t
PHL
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
50pF
SV00901
2.7–3.6V
2.7V
Figure 3. Load circuitry for switching times
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