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參數(shù)資料
| 型號(hào)： | 74LV20DB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 4-input NAND gate |
| 中文描述： | LV/LV-A/LVX/H SERIES, DUAL 4-INPUT NAND GATE, PDSO14 |
| 封裝： | PLASTIC, SSOP2-14 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 114K |
| 代理商： | 74LV20DB |
Philips Semiconductors
Product specification
74LV20
Dual 4-input NAND gate
2
1998 Apr 20
853–1962 19256
FEATURES
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
Typical V
OLP
(output ground bounce)
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot)
T
amb
= 25
°
C
Output capability: standard
I
CC
category: SSI
0.8V @ V
CC
= 3.3V,
2V @ V
CC
= 3.3V,
DESCRIPTION
The 74LV20 is a low–voltage Si–gate CMOS device and is pin and
function compatible with 74HC/HCT20.
The 74LV20 provides the 4–input NAND function.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
=t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nA, nB, nC, nD to nY
C
L
= 15pF
V
CC
= 3.3V
8
ns
C
I
C
PD
NOTES:
1
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
V
CC2
x f
i
(C
L
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC2
f
o
) = sum of the outputs.
2
The condition is V
I
= GND to V
CC
Input capacitance
3.5
pF
Power dissipation capacitance per gate
Notes 1 and 2
22
pF
V
CC2
f
o
) where:
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
14-Pin Plastic DIL
–40
°
C to +125
°
C
74LV20 N
74LV20 N
SOT27-1
14-Pin Plastic SO
–40
°
C to +125
°
C
74LV20 D
74LV20 D
SOT108-1
14-Pin Plastic SSOP Type II
–40
°
C to +125
°
C
74LV20 DB
74LV20 DB
SOT337-1
14-Pin Plastic TSSOP Type I
–40
°
C to +125
°
C
74LV20 PW
74LV20PW DH
SOT402-1
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 9
1A to 2A
Data inputs
2, 10
1B to 2B
Data inputs
3, 11
NC
No connection
4, 12
1C to 2C
Data inputs
5, 13
1D to 2D
Data inputs
6, 8
1Y to 2Y
Data outputs
7
GND
Ground (0V)
14
V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS
OUTPUTS
nY
H
H
H
H
L
nA
L
X
X
X
H
nB
X
L
X
X
H
nC
X
X
L
X
H
nD
X
X
X
L
H
NOTES:
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LV20 | Dual 4-input NAND gate |
| 74LV20D | Dual 4-input NAND gate |
| 74LV20N | Dual 4-input NAND gate |
| 74LV240 | Octal buffer/line driver; inverting (3-State)(反相, 八緩沖器/線驅(qū)動(dòng)器(三態(tài)）) |
| 74LV240D | Octal buffer/line driver; inverting 3-State |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV20DB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 4-input NAND Gate |
| 74LV20D-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 4-input NAND Gate |
| 74LV20N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 4-input NAND gate |
| 74LV20PW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 4-input NAND gate |
| 74LV20PWDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 4-input NAND gate |
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