參數(shù)資料
型號: 74LV165
廠商: NXP Semiconductors N.V.
英文描述: 8-bit parallel-in/serial-out shift register(8位并入串出移位寄存器)
中文描述: 8位parallel-in/serial-out移位寄存器(8位并入串出移位寄存器)
文件頁數(shù): 8/14頁
文件大?。?/td> 137K
代理商: 74LV165
Philips Semiconductors
Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07
8
AC WAVEFORMS
V
M
= 1.5 V at V
CC
2.7 V.
V
M
= 0.5
×
V
CC
at V
CC
<
2.7 V;
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
SV00592
D
7
INPUT
V
M
V
M
V
M
Q
7
OUTPUT
Q
7
OUTPUT
V
OL
V
OL
GND
V
OH
V
OH
V
I
t
PLH
t
PHL
t
PHL
t
PLH
Figure 3. Data input (D
n
) to output (Q
7
or Q
7
) propagation
delays when PL is LOW.
SV00595
V
M
V
M
CP, CE
INPUT
GND
D
S
INPUT
CP, CE
INPUT
GND
GND
V
I
V
I
V
I
stable
V
M
t
h
t
su
(H)
t
W
t
su
(L)
t
su
t
h
t
h
see note
CE may change only from HIGH-to-LOW while CP is LOW. The shaded
areas indicate when the input is permitted to change for predictable output
performance.
Figure 4. Set-up and hold times from the serial data input (D
S
) to
the clock (CP) and the clock enable (CE) inputs, from the clock
enable input (CE) to the clock input (CP) and from the clock input
(CP) to the clock enable input (CE).
Note to Figure 4
CE may change only from HIGH-to-LOW while CP is LOW. The
shaded areas indicate when the input is permitted to change for
predictable output performance.
SV00593
V
M
V
M
D
n
INPUT
PL INPUT
GND
GND
V
I
V
I
t
su
t
su
t
H
t
H
Figure 5. Set-up and hold times from the data inputs (D
n
)
to the parallel load input (PL).
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
l
D.U.T.
V
O
C
L
R
L
= 1k
V
cc
Test Circuit for Outputs
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitiance
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
V
CC
V
I
< 2.7V
2.7–3.6V
V
CC
2.7V
TEST
t
PLH/
t
PHL
4.5 V
V
CC
50pF
SV00902
Figure 6. Load circuitry for switching times.
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