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參數(shù)資料
| 型號： | 74LV164 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit serial-in/parallel-out shift register(8位串入并出移位寄存器) |
| 中文描述： | 8位serial-in/parallel-out移位寄存器（8位串入并出移位寄存器） |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 119K |
| 代理商： | 74LV164 |
Philips Semiconductors
Product specification
74LV164
8-bit serial-in/parallel-out shift register
1998 May 07
6
AC CHARACTERISTICS
GND = 0V; t
r
= t
f
≤
2.5ns; C
L
= 50pF; R
L
= 1K
SYMBOL
PARAMETER
WAVEFORM
CONDITION
LIMITS
–40 to +85
°
C
TYP
1
75
26
19
14
2
12
2
75
26
19
14
2
12
2
9
6
5
2
4
2
10
8
6
2
5
2
30
10
8
6
2
5
2
15
5
4
3
2
2
2
–10
–3
–2
–2
2
–1
2
40
58
70
2
100
2
LIMITS
–40 to +125
°
C
MIN
–
–
–
–
–
–
–
–
–
–
41
30
24
16
41
30
24
16
–
24
18
14
10
–
26
19
15
10
–
5
5
5
5
12
16
20
30
UNIT
V
CC
(V)
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.7
3.0 to 3.6
4.5 to 5.5
MIN
–
–
–
–
–
–
–
–
–
–
34
25
20
13
34
25
20
13
–
19
14
11
8
–
22
16
13
9
–
5
5
5
5
14
19
24
36
MAX
–
39
29
23
19
–
39
29
23
19
–
–
–
MAX
–
49
36
29
24
–
49
36
29
24
–
–
–
Propagation delay
CP to Q
n
t
PHL/
t
PLH
Figure 1
ns
Propagation delay
MR to Q
n
t
PHL
Figure 2
ns
t
W
Clock pulse width
HIGH to LOW
Figure 1
ns
–
–
–
–
–
–
t
W
Master reset pulse
width; LOW
Figure 2
ns
–
–
–
–
–
–
–
–
Removal time
MR to CP
t
rem
Figure 2
ns
–
–
–
–
–
–
–
–
Set up time
Set-up time
D
sa
, D
sb
to CP
t
su
Figure 3
ns
–
–
–
–
–
–
–
–
Hold time
D
sa
, D
sb
to CP
t
h
Figure 3
–
–
–
–
–
–
f
max
Maximum clock
pulse frequency
Figure 1
MHz
NOTE:
1. Unless otherwise stated, all typical values are at T
amb
= 25
°
C.
2. Typical value measured at V
CC
= 3.3V.
3. Typical value measured at V
CC
= 5.0V.
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