參數(shù)資料
型號(hào): 74LV163PWDH
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Presettable synchronous 4-bit binary counter; synchronous reset
中文描述: LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
文件頁數(shù): 4/14頁
文件大小: 142K
代理商: 74LV163PWDH
Philips Semiconductors
Product specification
74LV163
Presettable synchronous 4-bit binary counter;
synchronous reset
1998 Apr 30
4
FUNCTION TABLE
OPERATING MODES
INPUTS
OUTPUTS
MR
CP
CEP
CET
PE
D
n
X
Q
n
L
TC
Reset (clear)
l
X
X
X
L
Parallel load
h
X
X
I
I
L
L
h
X
X
I
h
H
*
Count
h
h
h
h
X
Count
*
Hold (do nothing)
h
X
I
X
h
X
q
n
q
n
*
h
X
X
I
h
X
L
NOTES:
*
=
H =
h
=
L
=
I
=
q
=
X =
=
The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH)
HIGH voltage level
HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
LOW voltage level
LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition
lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition
don’t care
LOW-to-HIGH clock transition
STATE DIAGRAM
SV00573
0
1
2
3
4
5
6
7
8
9
10
11
12
15
14
13
TYPICAL TIMING SEQUENCE
SV00582
MR
PE
D
0
D
1
D
2
D
3
CP
CEP
CET
Q
0
Q
1
Q
2
Q
3
TC
resetpreset
count
inhibit
13
14
15
0
1
2
12
Typical timing sequence: reset outputs to zero; preset to binary twelve; count to
thirteen, fourteen, fifteen, zero, one and two; inhibit
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