- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360485 > 74LV163D (NXP SEMICONDUCTORS) Presettable synchronous 4-bit binary counter; synchronous reset PDF資料下載
參數(shù)資料
| 型號(hào)： | 74LV163D |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Presettable synchronous 4-bit binary counter; synchronous reset |
| 中文描述： | LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 142K |
| 代理商： | 74LV163D |
Philips Semiconductors
Product specification
74LV163
Presettable synchronous 4-bit binary counter;
synchronous reset
1998 Apr 30
9
AC WAVEFORMS
V
M
= 1.5 V at V
CC
≥
2.7 V;
V
M
= 0.5
×
V
CC
at V
CC
<
2.7 V;
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
Q
n
, TC
OUTPUT
t
W
SV00576
V
M
CP INPUT
V
M
t
PLH
t
PHL
1/f
max
V
OL
V
OH
GND
V
I
Figure 1. Clock (CP) to outputs (Q
n
, TC) propagation delays,
the clock pulse width and the maximum clock frequency.
SV00578
V
M
CET INPUT
TC OUTPUT
V
M
t
PHL
t
PLH
GND
V
I
V
OL
V
OH
Figure 2. Input (CET) to output (TC) propagation delays and
output transition times.
SV00579
V
M
V
M
PE INPUT
CP INPUT
D
n
INPUT
V
M
t
h
t
su
t
su
t
su
t
su
t
h
t
h
t
h
GND
GND
GND
V
I
V
I
V
I
The shaded areas indicate when the input is permitted to change
for predictable output performance.
Figure 3. Set-up and hold times for input (D
n
)
and parallel enable input (PE).
SV00584
V
M
MR
INPUT
GND
CP INPUT
V
M
t
h
t
su
t
su
t
h
GND
V
I
V
I
The shaded areas indicate when the input is permitted to change
for predictable output performance.
Figure 4. MR set-up and hold times.
SV00580
V
M
CEP, CET
INPUT
CP INPUT
V
M
t
h
t
su
t
su
t
h
GND
GND
V
I
V
I
The shaded areas indicate when the input is permitted to change
for predictable output performance.
Figure 5. CEP and CET set-up and hold times.
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
R
L = 1K
V
CC
Test Circuit for switching times
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitance
V
CC
V
I
< 2.7V
V
CC
2.7V
TEST
t
PLH/
t
PHL
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
50pF
SV00901
2.7–3.6V
Figure 6. Load circuitry for switching times.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LV163N | Presettable synchronous 4-bit binary counter; synchronous reset |
| 74LV163PW | Presettable synchronous 4-bit binary counter; synchronous reset |
| 74LV163PWDH | Presettable synchronous 4-bit binary counter; synchronous reset |
| 74LV163DB | Presettable synchronous 4-bit binary counter; synchronous reset |
| 74LV164 | 8-bit serial-in/parallel-out shift register(8位串入并出移位寄存器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV163DB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Presettable synchronous 4-bit binary counter; synchronous reset |
| 74LV163DB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Up Counter |
| 74LV163D-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Up Counter |
| 74LV163N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Presettable synchronous 4-bit binary counter; synchronous reset |
| 74LV163PW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Presettable synchronous 4-bit binary counter; synchronous reset |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。