參數(shù)資料
型號: 74LV161
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: Presettable synchronous 4-bit binary counter; asynchronous reset
中文描述: 可預(yù)置同步4位二進(jìn)制計數(shù)器;異步復(fù)位
文件頁數(shù): 4/16頁
文件大小: 148K
代理商: 74LV161
Philips Semiconductors
Presettable synchronous 4-bit binary counter;
asynchronous reset
Product specification
74LV161
1997 May 15
4
FUNCTION TABLE
OPERATING MODES
INPUTS
OUTPUTS
MR
CP
CEP
CET
PE
D
n
X
Q
n
L
TC
Reset (clear)
L
X
X
X
X
L
Parallel load
H
X
X
I
I
L
L
H
X
X
I
h
H
*
Count
H
h
h
h
X
Count
*
Hold (do nothing)
H
X
I
X
h
X
q
n
q
n
*
H
X
X
I
h
X
L
NOTES:
*
=
H =
h
=
L
=
I
=
q
=
X =
=
The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH)
HIGH voltage level
HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
LOW voltage level
LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition
lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition
don’t care
LOW-to-HIGH clock transition
STATE DIAGRAM
SV00573
0
1
2
3
4
5
6
7
8
9
10
11
12
15
14
13
TYPICAL TIMING SEQUENCE
SV00574
MR
PE
D0
D1
D2
D3
CP
CEP
CET
Q0
Q1
Q2
Q3
TC
reset
preset
count
inhibit
13
14
15
0
1
2
12
Typical timing sequence: reset outputs to zero; preset to binary twelve;
count to thirteen, fourteen, fifteen, zero, on and two; inhibit.
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