參數(shù)資料
型號: 74LV157D
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Quad 2-input multiplexer
中文描述: LV/LV-A/LVX/H SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16
文件頁數(shù): 6/12頁
文件大?。?/td> 117K
代理商: 74LV157D
Philips Semiconductors
Product specification
74LV157
Quad 2-input multiplexer
1998 Apr 30
6
AC CHARACTERISTICS
GND = 0V; t
r
= t
f
= 2.5ns; C
L
= 50pF; R
L
= K
CONDITION
LIMITS
SYMBOL
PARAMETER
WAVEFORM
–40 to +85
°
C
TYP
1
65
22
16
12
2
70
24
18
13
2
75
26
19
14
2
–40 to +125
°
C
MIN
UNIT
V
CC
(V)
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
MIN
MAX
MAX
t
PHL/
t
PLH
Propagation delay
nl
0
to nY;
nl
to nY
1
Figures 1 2
Figures 1, 2
43
31
25
51
38
30
ns
t
PHL/
t
PLH
Propagation delay
E to nY
Figures 1 2
Figures 1, 2
44
33
26
54
40
32
ns
y
t
PHL/
PLH
t
Propagation delay
S to nY
Figures 1 2
Figures 1, 2
49
36
29
60
44
35
ns
NOTES:
1. Unless otherwise stated, all typical values are measured at T
amb
= 25
°
C
2. Typical values are measured at V
CC
= 3.3 V.
AC WAVEFORMS
V
M
= 1.5 V at V
CC
2.7 V;
V
M
= 0.5 V
×
V
CC
at V
CC
<
2.7 V.
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
SV00567
V
M
E INPUT
nY OUTPUT
V
M
t
PLH
t
PHL
GND
V
CC
V
OL
V
OH
Figure 1. Enable input (E) to output (nY)
propagation delays and output transition times.
SV00568
V
M
nI
0
, nI
1
, S
INPUT
nY OUTPUT
V
M
t
PLH
t
PHL
GND
V
CC
V
OL
V
OH
Figure 2. Data inputs (nl
n
) and common data select input (S) to
output (nY) propagation delays.
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
R
L
= 1k
V
CC
Test Circuit for switching times
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitance
V
CC
V
I
< 2.7V
V
CC
TEST
t
PLH/
t
PHL
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
50pF
SV00901
2.7–3.6V
2.7V
Figure 3. Load circuitry for switching times.
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