參數(shù)資料
型號: 74LV126
廠商: NXP Semiconductors N.V.
英文描述: Quad buffer/line driver 3-State
中文描述: 四緩沖器/線路驅(qū)動器三態(tài)
文件頁數(shù): 6/12頁
文件大?。?/td> 112K
代理商: 74LV126
Philips Semiconductors
Product specification
74LV126
Quad buffer/line driver (3-State)
1998 Apr 28
6
AC WAVEFORMS
V
M
= 1.5 V at V
CC
2.7 V and
3.6 V;
V
M
= 0.5
×
V
CC
at V
CC
<
2.7 V and
4.5 V;
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
V
X
= V
OL
+ 0.3 V at V
CC
2.7 V and
3.6 V;
V
X
= V
OL
+ 0.1
×
V
CC
at V
CC
< 2.7 V and
4.5 V.
V
Y
= V
OH
– 0.3 V at V
CC
2.7 V and
3.6 V;
V
Y
= V
OH
– 0.1
×
V
CC
at V
CC
< 2.7 V and
4.5 V.
SV00487
nA INPUT
nY OUTPUT
GND
VI
VOL
VOH
tPHL
tPLH
VM
VM
Figure 1.
Input (nA, nB) to output (nY) propagation delays
SV00488
outputs
disabled
outputs
enabled
outputs
enabled
tPHZ
tPZL
tPLZ
VX
VY
VM
VM
VM
nOE INPUT
VI
GND
VOL
VOH
GND
HIGOUTPUT
LOOUVCC
tPZH
Figure 2.
3-state enable and disable times.
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
R
L
= 1k
V
CC
Test Circuit for Outputs
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitiance.
V
CC
V
I
< 2.7V
V
CC
TEST
t
PLH/
t
PHL
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
2.7V
2.7–3.6V
4.5V
V
CC
50 pF
SV00896
S
1
t
PLZ/
t
PZL
t
PHZ/
t
PZH
Open
2 * V
CC
GND
R
L
= 1k
Open
GND
2 * V
CC
Figure 3.
Load circuitry for switching times.
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