參數(shù)資料
型號: 74LV125PWDH
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Quad buffer/line driver 3-State
中文描述: LV/LV-A/LVX/H SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
文件頁數(shù): 5/12頁
文件大小: 111K
代理商: 74LV125PWDH
Philips Semiconductors
Product specification
74LV125
Quad buffer/line driver (3-State)
1998 Apr 28
5
DC ELECTRICAL CHARACTERISTICS (Continued)
Over recommended operating conditions, voltages are referenced to GND (ground = 0 V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
-40
°
C to +85
°
C
TYP
1
-40
°
C to +125
°
C
MIN
UNIT
MIN
MAX
MAX
I
I
Input leakage
current
V
CC
= 5.5 V; V
I
= V
CC
or GND
1.0
1.0
μ
A
I
OZ
3-State output
OFF-state current
V
CC
= 5.5 V; V
I
= V
IH
or V
IL;
V
O
= V
CC
or GND
5
10
μ
A
I
CC
Quiescent supply
current; MSI
V
CC
= 5.5 V; V
I
= V
CC
or GND; I
O
= 0
20.0
160
μ
A
I
CC
Additional
quiescent supply
current per input
V
CC
= 2.7 V to 3.6 V; V
I
= V
CC
– 0.6 V
500
850
μ
A
NOTE:
1. All typical values are measured at T
amb
= 25
°
C.
AC CHARACTERISTICS
GND = 0V; t
r
= t
f
2.5ns; C
L
= 50pF; R
L
= 1K
CONDITION
LIMITS
SYMBOL
PARAMETER
WAVEFORM
–40 to +85
°
C
TYP
1
55
19
14
10
2
–40 to +125
°
C
MIN
UNIT
V
CC
(V)
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
MIN
MAX
MAX
Propagation delay
nA to nY
24
18
14
12
31
23
18
15
t
PHL/
t
PLH
Figures 1, 2
ns
75
26
19
14
2
3-State output
3 State out ut
enable time
nOE to nY
31
23
18
15
39
29
23
19
t
PZH/
t
PZL
Figures 2, 3
ns
65
24
18
14
2
3-State output
3 State out ut
disable time
nOE to nY
32
24
20
17
39
29
24
21
t
PHZ/
t
PLZ
Figures 2, 3
ns
NOTES:
1. Unless otherwise stated, all typical values are measured at T
amb
= 25
°
C
2. Typical values are measured at V
CC
= 3.3 V.
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