參數(shù)資料
型號: 74LV11DB
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Triple 3-input AND gate
中文描述: LV/LV-A/LVX/H SERIES, TRIPLE 3-INPUT AND GATE, PDSO14
封裝: PLASTIC, SSOP-14
文件頁數(shù): 5/10頁
文件大?。?/td> 113K
代理商: 74LV11DB
Philips Semiconductors
Product specification
74LV11
Triple 3-input AND gate
1998 Apr 20
5
DC CHARACTERISTICS FOR THE LV FAMILY (Continued)
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
-40
°
C to +85
°
C
-40
°
C to +125
°
C
I
CC
Quiescent supply
current; SSI
Additional
quiescent supply
current per input
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
20.0
40
μ
A
I
CC
V
CC
= 2.7V to 3.6V; V
I
= V
CC
– 0.6V
500
850
μ
A
NOTE:
1. All typical values are measured at T
amb
= 25
°
C.
AC CHARACTERISTICS
GND = 0V; t
r
= t
f
2.5ns; C
L
= 50pF; R
L
= 1K
CONDITION
LIMITS
SYMBOL
PARAMETER
WAVEFORM
–40 to +85
°
C
TYP
1
60
20
15
11
2
–40 to +125
°
C
MIN
UNIT
V
CC
(V)
1.2
2.0
2.7
3.0 to 3.6
MIN
MAX
MAX
t
PHL/PLH
Propagation delay
nA, nB, nC to nY
Figures 1 2
Figures 1, 2
39
29
23
46
34
27
ns
y
NOTES:
1. Unless otherwise stated, all typical values are measured at T
amb
= 25
°
C.
2. Typical values are measured at V
CC
= 3.3 V.
AC WAVEFORMS
V
M
= 1.5 V at V
CC
V
M
= 0.5
×
V
CC
at V
CC
< 2.7 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
2.7 V
SV00423
VM
nA, nB, nC INPUT
nY OUTPUT
VM
tPLH
tPHL
GND
V
l
VOL
VOH
Figure 1. Input (nA, nB, nC) to output (nY) propagation delays.
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
R
L
= 1k
V
CC
Test Circuit for switching times
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitance
V
CC
V
I
< 2.7V
V
CC
TEST
t
PLH/
t
PHL
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
50pF
SV00901
2.7–3.6V
2.7V
Figure 2. Load circuitry for switching times.
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