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參數(shù)資料
| 型號(hào)： | 74LV107 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual JK flip-flop with reset; negative-edge trigger |
| 中文描述： | 雙JK觸發(fā)器的復(fù)位觸發(fā)器，負(fù)邊沿觸發(fā) |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 121K |
| 代理商： | 74LV107 |
Philips Semiconductors
Product specification
74LV107
Dual JK flip-flop with reset; negative-edge trigger
1998 Apr 20
4
FUNCTION TABLE
OPERATING MODES
INPUTS
OUTPUTS
nR
nCP
nJ
nK
nQ
nQ
Asynchronous reset
L
X
X
X
L
H
Toggle
Load “0” (reset)
Load “1” (set)
Hold “no change”
NOTES:
H =
HIGH voltage level
h =
HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition
L =
LOW voltage level
I
=
LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition
q =
lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP transition.
X =
don’t care
↓
=
HIGH-to-LOW CP transition
H
H
H
H
↓
↓
↓
↓
h
l
h
l
h
h
l
l
q
L
H
q
q
H
L
q
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
I
IK
I
OK
DC supply voltage
–0.5 to +7.0
V
DC input diode current
V
I
< –0.5 or V
I
> V
CC
+ 0.5V
V
O
< –0.5 or V
O
> V
CC
+ 0.5V
20
mA
DC output diode current
50
mA
I
O
DC output source or sink current
– standard outputs
–0.5V < V
O
< V
CC
+ 0.5V
25
mA
I
GND
,
CC
T
stg
DC V
CC
or GND current for types with
– standard outputs
50
mA
Storage temperature range
–65 to +150
°
C
P
TOT
Power dissipation per package
– plastic DIL
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125
°
C
above +70
°
C derate linearly with 12 mW/K
above +70
°
C derate linearly with 8 mW/K
above +60
°
C derate linearly with 5.5 mW/K
750
500
400
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNIT
V
CC
V
I
V
O
DC supply voltage
See Note 1
1.0
3.3
5.5
V
Input voltage
0
–
V
CC
V
CC
+85
+125
V
Output voltage
0
–
V
T
amb
Operating ambient temperature range in free air
See DC and AC
characteristics
–40
–40
°
C
t
r
, t
f
Input rise and fall times except for
Schmitt-trigger inputs
V
CC
= 1.0V to 2.0V
V
CC
= 2.0V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V to 5.5V
–
–
–
–
–
–
–
–
500
200
100
50
ns/V
NOTE:
1. The LV is guaranteed to function down to V
CC
= 1.0V (input levels GND or V
CC
); DC characteristics are guaranteed from V
CC
= 1.2V to V
CC
= 5.5V.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LV107D | CMOS/TTL Compatible |
| 74LV107DB | CMOS |
| 74LV107N | Dual JK flip-flop with reset; negative-edge trigger |
| 74LV107PW | CLP SINE |
| 74LV107PWDH | CLP SINE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV107D | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual JK flip-flop with reset; negative-edge trigger |
| 74LV107DB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual JK flip-flop with reset; negative-edge trigger |
| 74LV107DB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| 74LV107D-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| 74LV107N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual JK flip-flop with reset; negative-edge trigger |
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