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參數(shù)資料
| 型號(hào)： | 74LS77 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4-BIT D LATCH LOW POWER SCHOTTKY |
| 中文描述： | 4位D鎖存低功耗肖特基 |
| 文件頁(yè)數(shù)： | 4/4頁(yè) |
| 文件大?。?/td> | 71K |
| 代理商： | 74LS77 |
5-4
FAST AND LS TTL DATA
SN54/74LS75 SN54/74LS77
LOGIC DIAGRAM
DATA
ENABLE
TO OTHER LATCH
Q (SN54/74LS75 ONLY)
Q
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°
C
IOH
IOL
Output Current — High
54, 74
–0.4
mA
Output Current — Low
54
74
4.0
8.0
mA
AC SETUP REQUIREMENTS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
b l
Parameter
Limits
U i
Unit
Test Conditions
di i
Min
Typ
Max
tW
ts
th
Enable Pulse Width High
20
ns
VCC = 5.0 V
5 0 V
Setup Time
20
ns
Hold Time
0
ns
AC WAVEFORMS
D
E
Q
Q
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
th
ts
tPLH
tPLH
tPHL
tPHL
tPLH
tPHL
tPHL
tPLH
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the
clock transition from HIGH-to-LOW in order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH-to-LOW that the logic level must be
maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may
be released prior to the clock transition from HIGH-to-LOW and still be recognized.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LS83 | 4-BIT BINARY FULL ADDER WITH FAST CARRY |
| 74LS83 | 4-Bit Binary Adder with Fast Carry |
| 74LS85 | LOW POWER SCHOTTKY |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LS794 WAFER | 制造商:Rochester Electronics LLC 功能描述: |
| 74LS794N | 制造商:Rochester Electronics LLC 功能描述: |
| 74LS794XC WAF | 制造商:Rochester Electronics LLC 功能描述: |
| 74LS83 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:4-BIT BINARY FULL ADDER WITH FAST CARRY |
| 74LS83 WAF | 制造商:Texas Instruments 功能描述: |
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