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參數(shù)資料
| 型號(hào)： | 74LCX245WMX |
| 廠商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 11/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANSCVR BIDIR 8BIT 20SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 74LCX |
| 邏輯類型： | 收發(fā)器，非反相 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 8 |
| 輸出電流高，低： | 24mA，24mA |
| 電源電壓： | 2 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 1211 (CN2011-ZH PDF) |
| 其它名稱： | 74LCX245WMXDKR |
CS35L01/03
DS909F1
9
ELECTRICAL CHARACTERISTICS - ALL OPERATIONAL MODES
Note:
6. No external loads should be connected to the LFILT+ net. Any connection of a load to this point may
result in errant operation or performance degradation in the device.
7. When VBATT is below this threshold (VBLIM), operation is automatically restricted to SD mode.
8. When operating in HD or FHD mode and the differential input voltage remains below the input level
threshold (VIN-LDO) for a period of time (tLDO), the PWM outputs will be powered by the internally
generated LDO supply (VLDO).
9. When operating in HD or FHD mode and the differential input voltage is above this input level
threshold (VIN-VBATT), the PWM outputs will be powered directly from the VBATT supply.
10. Refer to Section 5.5 for more information on Thermal Error functionality.
11. Under Voltage Lockout is the threshold at which a decreasing VBATT supply will disable device
operation.
Parameters
Symbol
Test Conditions
Min
Typ
Max Units
Max. Current from LFILT+
ILFILT+
-10
-
A
LFILT+ Output Impedance
ZLFILT+
-0.7
-
VBATT Limit for HD/FHD Mode
VBLIM
-3.0
-
VDC
Input Level for Entering LDO Operation in
HD/FHD Modes
VIN-LDO
CS35L03
CS35L01
-
0.015VBATT
0.029VBATT
-
Vrms
Input Level for Entering VBATT Operation in
HD/FHD Modes
VIN-VBATT
CS35L03
CS35L01
-
0.09
0.19
-
Vrms
LDO Entry Time Delay
tLDO
-
1200
-
ms
LDO Level for HD/FHD Modes
VLDO
-1.0
-
V
Output Offset Voltage
VOFFSET Inputs AC coupled to GND
-+/-1.5
-
mV
Amplifier Gain
AV
CS35L03
CS35L01
-
12
6
-
dB
Shutdown Supply Current
IA(SD)
SD = Low
-0.05
-
A
MOSFET On Resistance
RDS(ON) Ibias = 0.5 A
-270
-
m
Thermal Error Threshold
TTE
-150
-
C
Thermal Error Retry Time
RTE
-100
-
ms
Under Voltage Lockout Threshold
UVLO
-
2.0
-
V
Operating Efficiency
Output Levels at 10% THD+N
8
+
33
H
Load
VBATT = 5 VDC
-
92
-
%
VBATT = 3.7 VDC
-
91
-
%
4
+
33
H
Load
VBATT = 5 VDC
-
87
-
%
VBATT = 3.7 VDC
-
86
-
%
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