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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | 74LCX240MTC |
| 寤犲晢锛� | Fairchild Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 12/12闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC INVERTER DUAL 4-INPUT 20TSSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 73 |
| 绯诲垪锛� | 74LCX |
| 閭忚集椤炲瀷锛� | 閫嗚畩鍣紝绶╂矕鍣� |
| 闆昏矾鏁�(sh霉)锛� | 2 |
| 杓稿叆鏁�(sh霉)锛� | 4 |
| 鐗归粸锛� | 涓夋厠(t脿i) |
| 闆绘簮闆诲锛� | 2 V ~ 3.6 V |
| 闆绘祦 - 闈滄厠(t脿i)锛堟渶澶у€硷級锛� | 10µA |
| 杓稿嚭闆绘祦楂�锛屼綆锛� | 24mA锛�24mA |
| 閭忚集闆诲钩 - 浣庯細 | 0.7 V ~ 0.8 V |
| 閭忚集闆诲钩 - 楂橈細 | 1.7 V ~ 2 V |
| 椤嶅畾闆诲鍜屾渶澶� CL 鏅傜殑鏈€澶у偝鎾欢閬诧細 | 6.5ns @ 3.3V锛�50pF |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 20-TSSOP |
| 灏佽/澶栨锛� | 20-TSSOP锛�0.173"锛�4.40mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
9
Commercial Temperature Range
IDT72V8980 3.3V Time Slot Interchange
Digital Switch 256 x 256
tTAA
C4i
TX0-7
Bit Cell Boundary
5705 drw11
CCO
tTOH
tTAZ
tTZA
tXCD
tXCH
tTOH
TX0-7
tOED
ODE
TX0-7
5705 drw12
tOED
C4i
RX0-7
5705 drw13
Bit Cell Boundaries
tSIS
tSIH
Figure 7. Serial Outputs and External Control
Figure 8. Output Driver Enable
RS
TX
5705 drw14
tZDO
tZRS
tRSZ
tRPW
Figure 10. Reset
Figure 9. Serial Inputs
Symbol
Characteristics
Min.
Typ.(2)
Max.
Unit
Test Conditions
tTAZ
TX0-7 Delay - Active to High Z
30
45
ns
RL = 1K
(3), CL = 150pF
tTZA
TX0-7 Delay - High Z to Active
45
60
ns
CL = 150pF
tTAA
TX0-7 Delay - Active to Active
40
60
ns
CL = 150pF
tTOH
TX0-7 Hold Time
20
45
ns
CL = 150pF
tOED
Output Driver Enable Delay
45
60
ns
RL = 1K
(3), CL = 150pF
tXCH
External Control Hold Time
5
50
ns
CL = 150pF
tXCD
External Control Delay
15
30
ns
CL = 150pF
tSIS
Serial Input Setup Time
10
20
ns
tSIH
Serial Input Hold Time
10
20
ns
tRSZ
Reset to High Z
5
30
ns
tZRS
High Z to Reset
0
ns
tZDO
High Z to Valid Data
32
cycles
C4i cycles
tRPW
Reset Pulse Width
100
ns
RL = 1K
(3), CL = 150pF
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25
掳C and are for design aid only; not guaranteed and not subject to production testing.
3. High Impedance is measured by pulling to the appropriate rail with R
L, with timing corrected to cancel time taken to discharge CL.
AC ELECTRICAL CHARACTERISTICS (1)
SERIAL STREAM TIMING
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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| 74LCX240MTC_08 | 鍒堕€犲晢:FAIRCHILD 鍒堕€犲晢鍏ㄧū:Fairchild Semiconductor 鍔熻兘鎻忚堪:Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs |
| 74LCX240MTC_Q | 鍔熻兘鎻忚堪:绶╂矕鍣ㄥ拰绶氳矾椹�(q奴)鍕曞櫒 Octal Buff/Line Drv RoHS:鍚� 鍒堕€犲晢:Micrel 杓稿叆绶氳矾鏁�(sh霉)閲�:1 杓稿嚭绶氳矾鏁�(sh霉)閲�:2 妤垫€�:Non-Inverting 闆绘簮闆诲-鏈€澶�:+/- 5.5 V 闆绘簮闆诲-鏈€灏�:+/- 2.37 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MSOP-8 灏佽:Reel |
| 74LCX240MTCX | 鍔熻兘鎻忚堪:绶╂矕鍣ㄥ拰绶氳矾椹�(q奴)鍕曞櫒 Octal Buff/Line Drv RoHS:鍚� 鍒堕€犲晢:Micrel 杓稿叆绶氳矾鏁�(sh霉)閲�:1 杓稿嚭绶氳矾鏁�(sh霉)閲�:2 妤垫€�:Non-Inverting 闆绘簮闆诲-鏈€澶�:+/- 5.5 V 闆绘簮闆诲-鏈€灏�:+/- 2.37 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MSOP-8 灏佽:Reel |
| 74LCX240MTCX_NL | 鍔熻兘鎻忚堪:绶╂矕鍣ㄥ拰绶氳矾椹�(q奴)鍕曞櫒 FINISHED GOOD RoHS:鍚� 鍒堕€犲晢:Micrel 杓稿叆绶氳矾鏁�(sh霉)閲�:1 杓稿嚭绶氳矾鏁�(sh霉)閲�:2 妤垫€�:Non-Inverting 闆绘簮闆诲-鏈€澶�:+/- 5.5 V 闆绘簮闆诲-鏈€灏�:+/- 2.37 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MSOP-8 灏佽:Reel |
| 74LCX240MTR | 鍔熻兘鎻忚堪:绶╂矕鍣ㄥ拰绶氳矾椹�(q奴)鍕曞櫒 Octal Bus Buffer RoHS:鍚� 鍒堕€犲晢:Micrel 杓稿叆绶氳矾鏁�(sh霉)閲�:1 杓稿嚭绶氳矾鏁�(sh霉)閲�:2 妤垫€�:Non-Inverting 闆绘簮闆诲-鏈€澶�:+/- 5.5 V 闆绘簮闆诲-鏈€灏�:+/- 2.37 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MSOP-8 灏佽:Reel |
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