參數(shù)資料
型號: 74LCX16821MEA
廠商: Fairchild Semiconductor
文件頁數(shù): 2/8頁
文件大?。?/td> 0K
描述: IC FLIP FLOP 20BIT D LV 56SSOP
產(chǎn)品變化通告: Die Material/Mold Compound Change 10/Sept/2008
標準包裝: 25
系列: 74LCX
功能: 標準
類型: D 型總線
輸出類型: 三態(tài)非反相
元件數(shù): 2
每個元件的位元數(shù): 10
頻率 - 時鐘: 150MHz
延遲時間 - 傳輸: 6.2ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 24mA,24mA
電源電壓: 2 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-BSSOP(0.295",7.50mm 寬)
包裝: 管件
www.fairchildsemi.com
2
74LCX16821
Connection Diagram
Truth Tables
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
Z
= High Impedance
O0 = Previous O0 before LOW-to-HIGH transition of Clock
= LOW-to-HIGH transition
Functional Description
The LCX16821 contains twenty D-type flip-flops with 3-
STATE standard outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
20-bit operation. The following description applies to each
byte. The twenty flip-flops will store the state of their indi-
vidual D inputs that meet the setup and hold time require-
ments on the LOW-to-HIGH Clock (CLK) transition. The 3-
STATE standard outputs are controlled by the Output
Enable (OEn) input. When OEn is LOW, the standard out-
puts are in the 2-state mode. When OEn is HIGH, the stan-
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the flip-flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Outputs
CLK1
OE1
D0–D9
O0–O9
XH
X
Z
LL
L
LH
H
L or H
L
X
O0
Inputs
Outputs
CLK2
OE2
D10–D19
O10–O19
XH
X
Z
LL
L
LH
H
L or H
L
X
O0
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