參數(shù)資料
型號: 74HCT7404D
廠商: NXP SEMICONDUCTORS
元件分類: FIFO
英文描述: 5-Bit x 64-word FIFO register; 3-state
中文描述: 64 X 5 OTHER FIFO, 108 ns, PDSO20
封裝: PLASTIC, SO-20
文件頁數(shù): 2/28頁
文件大?。?/td> 131K
代理商: 74HCT7404D
September 1993
2
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
FEATURES
Synchronous or asynchronous operation
3-state outputs
30 MHz (typical) shift-in and shift-out rates
Readily expandable in word and bit dimensions
Pinning arranged for easy board layout: input pins
directly opposite output pins
Output capability: driver (8 mA)
I
CC
category: LSI.
APPLICATIONS
High-speed disc or tape controller
Communications buffer.
GENERAL DESCRIPTION
The 74HC/HCT7404 are high-speed Si-gate CMOS
devices specified in compliance with JEDEC standard
no.7A.
The “7404” is an expandable, First-In First-Out (FIFO)
memory organized as 64 words by 5 bits. A guaranteed
15 MHz data-rate makes it ideal for high-speed
applications. A higher data-rate can be obtained in
applications where the status flags are not used
(burst-mode).
With separate controls for shift-in (SI) and shift-out (SO),
reading and writing operations are completely
independent, allowing synchronous and asynchronous
data transfers. Additional controls include a master-reset
input (MR), an output enable input (OE) and flags. The
data-in-ready (DIR) and data-out-ready (DOR) flags
indicate the status of the device.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns.
Note
1.
For HC the condition is V
I
= GND to V
CC
.
For HCT the condition is V
I
= GND to V
CC
1.5 V.
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
HC
HCT
t
PHL
/t
PLH
f
max
C
I
C
PD
propagation delay SO, SI to DIR and DOR
maximum clock frequency
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V
15
30
3.5
475
17
30
3.5
490
ns
MHz
pF
pF
note 1
EXTENDED
TYPE NUMBER
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
74HC/HCT7404N
74HC/HCT7404D
18
20
DIL
SO20
plastic
plastic
SOT102
SOT163A
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