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參數(shù)資料
| 型號： | 74HCT7273 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual 4-Input Positive-NAND Gates 14-SO -40 to 85 |
| 中文描述： | 八路D型觸發(fā)器的復(fù)位觸發(fā)器，上升沿觸發(fā);開漏輸出 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大小： | 91K |
| 代理商： | 74HCT7273 |
1999 Oct 01
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
Exceeds 2000 V
MM EIA/JESD22-A115-A
Exceeds 200 V
Ideal buffer for MOS
microprocessor or memory
Eight positive edge-triggered
D-type flip-flops
Common clock and master reset
Output capability: standard (open
drain)
I
CC
category: MSI.
DESCRIPTION
The 74HCT7273 is a high-speed SI-gate CMOS device and is pin compatible
with Low power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard no 7A.
The 74HCT7273 has eight edge-triggered D-type flip-flops with individual D
inputs and Q outputs. The common Clock (CP) and Master Reset (MR) inputs
load and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding output (Q
n
) of the flip-flop.
ALOWlevelonthe MRinput forcesall outputsLOW,independently of theclock
or data inputs.
The device is useful for applications requiring true outputs only and clock and
master reset inputs that are common to all storage elements.
The 74HCT7273 has open-drain N-outputs, which are clamped by a diode
connected to V
CC
. When a HIGH is clocked in the flip-flop, the output comes in
the high-impedance OFF-state. The output may now be pulled to any voltage
between GND and V
Omax
. This allows the device to be used as a LOW-to-HIGH
or HIGH-to-LOW level shifter. For digital operation and OR-tied output
applications, the device must have a pull-up resistor to establish a logic HIGH
level.
QUICK REFERENCE DATA
Ground = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) +
∑
(V
02
/R
L
)
×
duty factor LOW where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
R
L
= pull-up resistor in M
;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
1.5 V.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PZL
/t
PLZ
propagation delay
CP to Q
n
MR to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance
C
L
= 50 pF; V
CC
= 4.5 V
16
23
56
3.5
37
ns
ns
MHz
pF
pF
f
max
C
I
C
PD
C
L
= 50 pF; f = 1 MHz; notes 1 and 2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HCT7273(SMD) | 制造商:MISCELLANEOUS 功能描述: |
| 74HCT7273D | 功能描述:觸發(fā)器 OCTAL D FF POS-EDGE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HCT7273D,112 | 功能描述:觸發(fā)器 OCTAL D FF POS-EDGE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HCT7273D,118 | 功能描述:觸發(fā)器 OCTAL D FLIP-FLOP RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HCT7273D-T | 功能描述:觸發(fā)器 OCTAL D FLIP-FLOP RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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